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module IF2ID(clk, next_PC_address, opcode, A_Reg, B_Reg, W_Reg, Sign, freeze, flush, | |
next_PC_address_O, opcode_O, A_Reg_O, B_Reg_O, W_Reg_O, Sign_O); | |
input clk; | |
input [7:0] next_PC_address; | |
input [3:0] opcode; | |
input [3:0] A_Reg; | |
input [3:0] B_Reg; | |
input [3:0] W_Reg; | |
input [3:0] Sign; | |
input freeze, flush; | |
output reg [7:0] next_PC_address_O; | |
output reg [3:0] opcode_O; | |
output reg [3:0] A_Reg_O; | |
output reg [3:0] B_Reg_O; | |
output reg [3:0] W_Reg_O; | |
output reg [3:0] Sign_O; | |
always @(negedge clk)begin | |
if(~freeze)begin | |
if(flush)begin | |
next_PC_address_O <= 7'bx; | |
opcode_O <= 3'bx; | |
A_Reg_O <= 3'bx; | |
B_Reg_O <= 3'bx; | |
W_Reg_O <= 3'bx; | |
Sign_O <= 3'bx; | |
end | |
else begin | |
next_PC_address_O <= next_PC_address; | |
opcode_O <= opcode; | |
A_Reg_O <= A_Reg; | |
B_Reg_O <= B_Reg; | |
W_Reg_O <= W_Reg; | |
Sign_O <= Sign; | |
end | |
end | |
end | |
endmodule |
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module IF_ID(clk, reset, select_line, new_address, pc_select, | |
opcode, A_reg_address, B_reg_address, W_reg_address, Sign, pc_to_im, next_pc_address); | |
input clk, reset; | |
input select_line; | |
input [7:0]new_address; | |
input pc_select; | |
output [3:0]opcode; | |
output [3:0]A_reg_address; | |
output [3:0]B_reg_address; | |
output [3:0]W_reg_address; | |
output [3:0]Sign; | |
output [7:0]pc_to_im; | |
output [7:0]next_pc_address; | |
wire [7:0] pc_out; | |
wire [7:0] pc_in, pc_to_im, next_pc_address; | |
//PC_ADD adder(pc_to_im,next_pc); | |
assign next_pc_address = pc_to_im + 2; | |
MUX8 mux4(next_pc_address, new_address, select_line, pc_in); | |
//module PC(in,clk,pc_select,out); | |
PC P_Counter(pc_in, clk, pc_select, reset, pc_to_im); | |
//module IF_Stage(in,out,clk,pc_select,opcode,A_reg,B_reg,W_reg,Sign); | |
IM Instruction_Mem(pc_to_im, clk, reset, opcode, A_reg_address, B_reg_address, W_reg_address, Sign); | |
endmodule |
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module IM(in,clk, reset, opcode, A_reg, B_reg, W_reg, Sign); | |
input [7:0]in; | |
input clk, reset; | |
reg [3:0]dest; | |
output [3:0]opcode; | |
output [3:0]A_reg; | |
output [3:0]B_reg; | |
output [3:0]W_reg; | |
output [3:0]Sign; | |
reg [7:0] imem[0:19]; | |
reg [15:0] instruction; | |
reg [8:0]temp; | |
always @(*)begin | |
if(reset) begin | |
imem[0]=8'b0001_0001; //0000 | |
imem[1]=8'b0010_0001; | |
imem[2]=8'b0010_0101; //0010 | |
imem[3]=8'b0101_0010; | |
imem[4]=8'b0011_0111; //0100 | |
imem[5]=8'b0111_0100; | |
imem[6]=8'b0100_0110; //0110 | |
imem[7]=8'b0101_0110; | |
imem[8]=8'b0101_1010; //1000 | |
imem[9]=8'b0111_0101; | |
imem[10]=8'b0110_0001; //1010 | |
imem[11]=8'b0100_0110; | |
imem[12]=8'b1110_0010; //1100 | |
imem[13]=8'b0011_0111; | |
imem[14]=8'b1111_0001; //1110 | |
imem[15]=8'b0100_0010; | |
//imem[16]=8'b0001_0001; //1100 | |
//imem[17]=8'b0100_1011; | |
end | |
end | |
assign A_reg = imem[in][3:0]; | |
assign opcode = imem[in][7:4]; | |
assign B_reg = imem[in+1][7:4]; | |
assign W_reg = imem[in+1][3:0]; | |
assign Sign = imem[in+1][3:0]; | |
endmodule | |
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module MUX8(a,b,sel,e); | |
input [7:0] a; | |
input [7:0] b; | |
input sel; | |
output reg [7:0]e; | |
always @(*)begin | |
if(sel) | |
e = b; | |
else | |
e = a; | |
end | |
endmodule |
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module PC(in,clk,pc_select,reset,out); | |
input [7:0]in; | |
input pc_select, clk,reset; | |
output reg[7:0]out; | |
//output [7:0]next_out; | |
initial begin | |
//out = 8'b11111110; | |
end | |
reg [8:0]temp; | |
always @(negedge clk)begin | |
if(reset) | |
out <= 0; | |
else if(pc_select)begin | |
out <= in; | |
end | |
end | |
endmodule |
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