P_EXE_Pipeline.v

module EXE2WB(clk, WB, mem_out, alu_result, mux1_w_reg, mux1_w_reg_O, alu_O, mem_out_O, mux3, regwrt
    );
input clk;
input [1:0] WB;
input [7:0] mem_out;
input [7:0] alu_result;
input [3:0] mux1_w_reg;

output reg [3:0] mux1_w_reg_O;
output reg [7:0] alu_O, mem_out_O;
output reg mux3;
output reg regwrt;

always @(negedge clk)begin
mux1_w_reg_O <=  mux1_w_reg;
alu_O <= alu_result;
mem_out_O <= mem_out;
mux3 <= WB[1];
regwrt <= WB[0];
end



endmodule

P_MEM_Stage.v

module MEM_WB(clk, read, write, Branch, alu_result, Data_for_RAM, zero, carry, mem_data, Branch_O);

input clk;
input zero, carry;
input [3:0] Branch;
input read, write;
input [7:0] alu_result, Data_for_RAM;

output [7:0]mem_data;
output [3:0] Branch_O;

//module MEM_Stage(clk,address,data_in,data_out,re,wr);
MEM_Stage Memory (clk, alu_result, Data_for_RAM, mem_data, read, write);

wire p, q, r, s;
and a(p, Branch[3], zero);
and b(q, Branch[2], ~zero);
and c(r, Branch[1], carry);
and d(s, Branch[0], ~carry);

assign Branch_O = {p, q, r, s};

endmodule

P_Memory_Unit.v

module MEM_Stage(clk,address,data_in,data_out,re,wr);
input [7:0]address;
input [7:0]data_in;
input clk,re,wr;
output [7:0]data_out;
reg[7:0] mem [0:30];

initial begin
mem[4]=15;
mem[7]=14;
end

always @(negedge clk)begin
if(wr)
mem[address] <= data_in;
end

assign data_out=re?mem[address]:0;

endmodule