16_Bit_Risc_IM.v

	module INSTRUCTION_MEMORY(address,clk,opcode,A_reg,B_reg,W_reg,Sign);
input [7:0]address;
input clk;
reg [3:0]dest;
output reg [3:0]opcode;
output reg [3:0]A_reg;
output reg [3:0]B_reg;
output reg [3:0]W_reg;
output reg [3:0]Sign;
reg [7:0] imem[0:17];
reg [15:0] instruction; 
initial begin
imem[0]<=8'b0100_0011; 
imem[1]<=8'b0111_0010;

imem[2]<=8'b0101_0010;
imem[3]<=8'b0001_0011; 

imem[4]<=8'b0011_0100;
imem[5]<=8'b0010_0011;

imem[6]<=8'b0100_0000;
imem[7]<=8'b0001_0010;

imem[8]<=8'b0101_0111;
imem[9]<=8'b0010_0010;

imem[10]<=8'b0110_0010;
imem[11]<=8'b0001_0010;

imem[12]<=8'b0111_0001;
imem[13]<=8'b0001_0011;

imem[14]<=8'b1000_0110;
imem[15]<=8'b0001_0011;

imem[16]<=8'b1001_0001;
imem[17]<=8'b0011_0001; 


end

always @(negedge clk)begin
	instruction = {imem[address],imem[address+1]};
	opcode = instruction[15:12];
	A_reg = instruction[11:8];
	B_reg = instruction[7:4];
	W_reg = instruction[3:0];
	Sign = instruction[3:0];
end

endmodule

16_Bit_Risc_PC.v

module PC(in,pc_select,clk,out);
input [7:0]in;
input clk,pc_select;
output reg [7:0]out;
initial begin
out = 0;
end
reg [8:0]temp;
always @(posedge pc_select)begin
	temp = in + 2;
	out = temp[7:0];
end
endmodule

16_Bit_Risc_Register.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:24:21 03/20/2019 
// Design Name: 
// Module Name:    REGISTER_FILE 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module REGISTER_FILE(clk,readA,readB,dest,data,reg_wrt,readA_out,readB_out);
input reg_wrt;
input [3:0]readA,readB,dest;
input [7:0]data;
input clk;
reg [7:0] Register [0:15];
initial begin
Register[0]=0;//R0 alwayscontains zero
Register[1]=2;  //Random values stored
Register[2]=4;
Register[3]=6;
Register[4]=8;
Register[5]=10; // You can change any value within this initial block
Register[6]=12;
Register[7]=14;
end
output reg [7:0]readA_out,readB_out;
always @(negedge clk)begin
readA_out <= Register[readA];
readB_out <= Register[readB];
if(reg_wrt==1)
	Register[dest]<=data;
end

endmodule

adder.v

module ADDER(A,B,out,clk);
input [7:0] A,B;
input clk;
output reg [7:0] out;
reg [7:0] temp;
always @(negedge clk)begin
	temp = B<<1;
	out = A + temp - 2;
end
endmodule

Sign_Xtend.v

module SIGN(a,b);
input [3:0]a;
output reg [7:0]b;
always @(a or b)begin
if(a[3]==1)
b = {4'b1111,a};
else
b = {4'b0000,a};
end
endmodule