MOD 5 UP COUNTER

MOD_5_UP_Counter.v

//********D Flip Flop**************//
module D1(Di,Q, Qb, clk, clear);
input Di, clk, clear;
output reg Q, Qb;
initial begin
Q = 0;
Qb = ~Q;
end

always @(posedge clk or posedge clear)begin
	if(clear)begin
	$display("Clear is %b and Qb is %b %b",clear, Qb, Q);
	Qb <= 0;
	Q <= 1;
	end
	else begin
	Qb <= ~Di;
	Q <= Di;
	end
end
endmodule


//************************Data Path************************//

module Path(OutA, clk);

input clk;
output [2:0]OutA;


wire D, Q, Dn;
wire c1,c2,c3;
D1 D11(Qb, Q, Qb, clk, c1);
D2 D22(Qb2, Q2, Qb2, Q, c1);
D3 D33(Qb3, Q3, Qb3, Q2, c1);

and #1 an(c1, Qb3, Qb);

assign OutA = {Qb3,Qb2,Qb};

endmodule

//********************TestBench**********************//
module DTest;

	// Inputs
	reg clk;

	// Outputs
		/*wire [0:0]Qb3;
		wire [0:0]Qb2;*/



	wire [2:0]Out;
	// Instantiate the Unit Under Test (UUT)
	Path uut (
		//.Out(Out),
		.clk(clk),
		.OutA(Out)
		//.OutB(Qb2),
		//.OutC(Qb)
	);

	initial begin
		// Initialize Inputs
		clk = 0;

		// Wait 100 ns for global reset to finish
       
		// Add stimulus here

	end
      
	always #2 clk = ~clk;
endmodule