P_Mux3.v

module MUX3(a,b,sel,c);
input [7:0] a,b;
input sel;
output reg [7:0]c;
always @(*)begin
if(sel==0)
c = a;
else
c = b;
end
endmodule

P_WB_Stage.v

module WB(mux3_select, mem_data, alu_result, mux1_in, W_data, W_add
    );

input mux3_select;
input [3:0]mux1_in;
input [7:0] mem_data;
input [7:0] alu_result;
output [7:0]W_data;
output [3:0]W_add;


assign W_add = mux1_in;

MUX3 mul1(mem_data, alu_result, mux3_select, W_data);

endmodule