16_Bit_Risc_Mux1.v

module MUX1(a,b,sel,c);

input [3:0] a,b;

input sel;

output reg [3:0]c;

always @(*)begin

if(sel==0)

c = a;

else

c = b;

end

endmodule

Mux2.v

module MUX2(a,b,sel,c);
input [7:0] a,b;
input sel;
output reg [7:0]c;
always @(*)begin
if(sel==0)
c = a;
else
c = b;
end
endmodule

Mux3.v

module MUX3(a,b,sel,c);
input [7:0] a,b;
input sel;
output reg [7:0]c;
always @(*)begin
if(sel==0)
c = a;
else
c = b;
end
endmodule

Mux4.v

module MUX4(a,b,sel,c);
input [7:0] a;
input [7:0] b;
input sel;
output reg [7:0]c;
always @(*)begin
if(sel==1'b0)
c = a;
else
c = b;
end
endmodule

Mux5.v

module MUX4(a,b,sel,c);
input [7:0] a;
input [7:0] b;
input sel;
output reg [7:0]c;
always @(*)begin
if(sel==1'b0)
c = a;
else
c = b;
end
endmodule

Mux6.v

module MUX4(a,b,sel,c);
input [7:0] a;
input [7:0] b;
input sel;
output reg [7:0]c;
always @(*)begin
if(sel==1'b0)
c = a;
else
c = b;
end
endmodule

Mux7.v

module MUX4(a,b,sel,c);
input [7:0] a;
input [7:0] b;
input sel;
output reg [7:0]c;
always @(*)begin
if(sel==1'b0)
c = a;
else
c = b;
end
endmodule

Mux8.v

module MUX8(a,b,c,d,f,g,sel,e);
input [7:0] a;
input [7:0] b;
input [7:0] c;
input [7:0] d;
input [7:0] f;
input [7:0] g;
input [3:0]sel;
output reg [7:0]e;
always @(*)begin
case(sel)
4'b1000:
e = b; //out
4'b0100:
e = c;
4'b0010:
e = d;
4'b0001:
e = f;
4'b0000:
e = a;
default:
e = g;
endcase
end
endmodule