RTL_I2C_Slave.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:        www.Hellocodings.com
// Engineer: 		 Shashi Suman
// 
// Create Date:    17:26:45 12/24/2018 
// Design Name: 	 Slave_Module
// Module Name:    Slave 
// Project Name: 	 I2C Protocol
// Target Devices: Spartan 6
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Slave(scl_m,sda);
input scl_m;
inout sda;

reg [6:0]address = 7'b1000001;
reg [6:0]temp_address_store;
reg [7:0]temp_reg;
reg [7:0]internal_reg = 8'b10101011;
reg [7:0]int_reg;
reg [4:0]count;
reg direction;
reg sda_val;
reg read;
reg scl;
reg add;
reg add_reg;
reg [7:0]data;

initial begin
direction = 0;
count = 0;
data = 8'b01101100;
end

always @(scl_m)begin
#2 scl <= scl_m;
end

always @(negedge scl)begin
	count = count + 1;
	if(count < 9)begin
		if(count < 8)begin
			temp_address_store = temp_address_store << 1;
			temp_address_store[0] = sda;
		end
		if(count == 8 && temp_address_store==address)
			add = 1;
		else
			add = 0;
		
	end
	else if(count == 9)begin
		direction = 1;
		if(add == 1)
			sda_val = 1;
		else begin
			sda_val = 0;
		end
	end
	//
	else if(count == 10)begin
		if(add == 0)begin
			count = 1;
			direction = 0;
			temp_address_store = 7'bxxxxxxx;
		end
		else begin
			temp_reg = temp_reg << 1;
			temp_reg[0] = sda;
			direction = 0;
		end
	end
	//
	else if(count >10 && count <18)begin
		temp_reg = temp_reg << 1;
		temp_reg[0] = sda;
		if (temp_reg == internal_reg)
			add_reg = 1;
		else
			add_reg = 0;
	end
	else if(count == 18 && add_reg == 1)begin
		direction = 1;
		sda_val = 1;
	end
	else if(count >18 && count<27)begin
		sda_val = data[7];
		data = data << 1;
	end
	else if(count == 27)begin
		direction = 0;
	end
	else begin
		direction = 0;
	end
end


assign sda = direction?sda_val:1'bZ;
endmodule

RTL_I2C_Test.v

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:50:33 12/24/2018
// Design Name:   Master
// Module Name:   C:/Users/Shashi Suman/Desktop/My/I2C/Tset.v
// Project Name:  I2C
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Master
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Tset;

	// Inputs
	reg clk;

	// Outputs
	wire scl;

	// Bidirs
	wire sda;

	// Instantiate the Unit Under Test (UUT)
	Master uut (
		.clk(clk), 
		.sda(sda), 
		.scl(scl)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		// Wait 100 ns for global reset to finish
	
        
		// Add stimulus here

	end
always #2 clk = ~clk; 
endmodule