fpgaread.v

module fpgaread(ARDUINOclk, FPGAclk, FPGAdata);

input ARDUINOclk;
output reg FPGAdata;
output reg FPGAclk;


reg [15:0] count= 16'd0;
reg [127:0] t = 128'd3542638353836;

//Counter
always @ (posedge ARDUINOclk) begin
    if (count < 16'd256) begin
        count <= count + 16'd1;
    end else begin
        count <= 16'd0;
    end
end

//External interface
always @ (posedge ARDUINOclk) begin
    if (!count[0]) begin //see if it is even by checking the LSB. You can use %2 if you want, but in complex cases it can infer horrid logic.
        FPGAclk <= 1'b0; //Falling edge
    end else if (count < 16'd256) begin
        FPGAclk <= 1'b1; //Rising edge
        FPGAdata <= t[count[15:1]]; //data goes out on rising edge.
    end
end

endmodule