Skip to content

Instantly share code, notes, and snippets.

Avatar

The6P4C The6P4C

View GitHub Profile
View lut-reading-materials.md
View RISC-V.md

Foreward

This document was originally written several years ago. At the time I was working as an execution core verification engineer at Arm. The following points are coloured heavily by working in and around the execution cores of various processors. Apply a pinch of salt; points contain varying degrees of opinion.

It is still my opinion that RISC-V could be much better designed; though I will also say that if I was building a 32 or 64-bit CPU today I'd likely implement the architecture to benefit from the existing tooling.

Mostly based upon the RISC-V ISA spec v2.0. Some updates have been made for v2.2

Original Foreword: Some Opinion

The RISC-V ISA has pursued minimalism to a fault. There is a large emphasis on minimizing instruction count, normalizing encoding, etc. This pursuit of minimalism has resulted in false orthogonalities (such as reusing the same instruction for branches, calls and returns) and a requirement for superfluous instructions which impacts code density both in terms of size and

View with_lennyface.py
import contextlib
@contextlib.contextmanager
def lennyface():
global print
oldprint = print
def new_print(*args, **kwargs):
#newargs = [a.replace(' ', '( ͡° ͜ʖ ͡°)') for a in args]
args = list(args)
You can’t perform that action at this time.