sub.v

module sub(i_clk, r, ce, a, b);
	parameter	N = 64;
	input	wire	i_clk, r, ce, a;
	output	wire	b;

	reg	[(N-1):0]	pipe;
	initial	pipe = 0;
	always @(posedge i_clk, posedge r)
		if (r)
			pipe <= 0;
		else if (ce)
			pipe <= { pipe[(N-2):0], a };

	assign	b = pipe[N-1];

endmodule

top.v

module top(i_clk, r, ce, a, b);
	input	wire i_clk, a, r, ce;
	output	wire	b;

	wire	s1, s2;

	sub sub1(i_clk, r, ce, a, s1);
	sub sub2(i_clk, r, ce, a, s2);

	assign	b = (s1 ^ s2);

	initial	assume(r);
	initial	assume(a==0);
	always @(posedge i_clk)
		assert(b == 0);

endmodule