result

$ yosys -q -p "synth_ice40 -top top -json top.json" top.v
$ nextpnr-ice40 --hx8k --package tq144:4k --json top.json --pcf top.pcf --asc top.asc
Info: Importing module top
Info: Rule checker, Verifying pre-placed design
Info: Checksum: 0xc43eb04e

Info: constrained 'LED1' to bel 'X31/Y0/io0'
Info: constrained 'CLK_OSC100' to bel 'X16/Y33/io1'

Info: Packing constants..
Info: Promoting globals..
Info: promoting clk
Info: Packing IOs..
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Packing carries..
Info: Packing RAMs..
Info: Packing special functions..
ERROR: PLL 'pll' PACKAGEPIN is connected to pin 129, can only be pin 49
ERROR: Packing design failed.


$ yosys -q -p "synth_ice40 -blif top.blif" top.v
$ arachne-pnr -d 8k -P tq144:4k -p top.pcf top.blif -o top.txt
seed: 1
device: 8k
read_chipdb +/share/arachne-pnr/chipdb-8k.bin...
  supported packages: bg121, bg121:4k, cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k
read_blif top.blif...
prune...
read_pcf top.pcf...
instantiate_io...
pack...

After packing:
IOs          1 / 107
GBs          0 / 8
  GB_IOs     0 / 8
LCs          27 / 7680
  DFF        3
  CARRY      2
  CARRY, DFF 22
  DFF PASS   0
  CARRY PASS 1
BRAMs        0 / 32
WARMBOOTs    0 / 1
PLLs         1 / 2

place_constraints...
promote_globals...
  promoted clk, 25 / 25
  promoted 1 nets
    1 clk
  1 globals
    1 clk
realize_constants...
  realized 1
place...
  initial wire length = 209
  at iteration #50: temp = 10.0697, wire length = 108
  at iteration #100: temp = 4.91074, wire length = 40
  at iteration #150: temp = 1.27103, wire length = 17
  final wire length = 11

After placement:
PIOs       2 / 107
PLBs       7 / 960
BRAMs      0 / 32

  place time 0.02s
route...
  pass 1, 0 shared.

After routing:
span_4     5 / 29696
span_12    0 / 5632

  route time 0.02s
write_txt top.txt...

top.pcf

set_io LED1 70
set_io CLK_OSC100 129

top.v

module top (
    input CLK_OSC100,
    output LED1
);

wire clk;

SB_PLL40_PAD #(
    .FEEDBACK_PATH("SIMPLE"),
    .DIVR(4'b0100),
    .DIVF(7'b0101111),
    .DIVQ(3'b101),
    .FILTER_RANGE(3'b010)
) pll (
    .RESETB(1'b1),
    .BYPASS(1'b0),
    .PACKAGEPIN(CLK_OSC100),
    .PLLOUTCORE(clk)
);

reg [24:0] count;
assign LED1 = count[24];

always @(posedge clk) begin
    count <= count + 1;
end

endmodule