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Adam Greig adamgreig

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adamgreig /
Created May 17, 2020
check stm32f3 patches for correct exti values
import sys
import os.path
import yaml
MAP = yaml.safe_load("""
3: a b c
2: a b c d
1: a b c f
View nand.rkt
#lang rosette/safe
(require rosette/lib/angelic rosette/lib/match)
; Circuit building block: NAND gates only
(struct nand (x y) #:transparent)
(define (interpret p)
(match p
[(nand x y) (not (and (interpret x) (interpret y)))]
[_ p]))
adamgreig /
Created Oct 9, 2018 — forked from tangrs/
Convert a memory dump/raw binary image into an ELF file
# Convert a raw binary image into an ELF file suitable for loading into a disassembler
cat > raw$$.ld <<EOF
echo " . = $3;" >> raw$$.ld
import traceback
from binaryninja import (BinaryView, Architecture, SegmentFlag, log_error,
get_address_input, log_info, SectionSemantics)
offset = 0x08000000
entry_addr = 0x080001c0
class FwImgView(BinaryView):
adamgreig /
Created Dec 14, 2017
AXI3 read-only slave in migen for Cyclone V SoC
from migen import Module, Signal, FSM, If, NextState, NextValue
class AXI3SlaveReader(Module):
AXI3 read-only slave.
Input signals are from the AXI3 master AR and R ports.
`regfile` is an Array which is indexed to respond to reads.
import sys
import time
import socket
import datetime
import numpy as np
import matplotlib.pyplot as plt
if len(sys.argv) != 4:
print("Usage: <Channel> <Max Voltage> <Voltage Step>")
View fir.v
`timescale 10ns / 1ns
module FIR
input reset,
input clock,
input [11:0] u,
output [11:0] y
import io
import sys
import time
import socket
import struct
from PIL import Image
if len(sys.argv) != 2:
print("Usage: <filename>")
adamgreig / Makefile
Last active Aug 29, 2015
BladeRF 10MHz Clock Output
View Makefile
gcc -g -c main.c -Wall -Werror -Wpedantic
gcc -g main.o -lpthread -lm -lbladeRF -Wall -Werror -Wpedantic -o bladerf-10mhz
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