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Created November 2, 2023 00:11
/// Extract the specified fields from the `Peripherals` struct into several named
/// structs which can be passed to other tasks to provide them with all their
/// resources, including pins, peripherals, DMA channels, etc.
/// The `peripherals` module must be in scope when `resource_assigs!{}` is called,
/// and it defines a new macro `split_resources!()` which uses the `Peripherals` struct
/// and returns a new struct with a field for each of the structs named in `resource_assigs!{}`.
/// Defines new structs containing the specified structs from the `peripherals` module,
/// a top-level struct that contains an instance of each of these new structs, and a macro
#!/usr/bin/env python3
import re
import sys
import time
import subprocess
import multiprocessing
import termplotlib as tpl
import numpy as np
import subprocess
import nmigen as nm
from import Resource, Pins, PinsN, Attrs, Clock, Subsignal
from nmigen.vendor.lattice_ecp5 import LatticeECP5Platform
class UART(nm.Elaboratable):
def __init__(self, data, divider=217, n=8):
assert divider >= 1
self.valid = nm.Signal()
Takes an ecpunpack output .config file and a iodb.json and works out attributes
set for each package pin as best it can.
LFE5U-25F-xBG256 only.
import re
import sys
import json
import io
import sys
import time
import socket
import struct
from PIL import Image
if len(sys.argv) != 3:
print("Usage: <IP address> <filename>")
adamgreig /
Created May 17, 2020 20:07
check stm32f3 patches for correct exti values
import sys
import os.path
import yaml
MAP = yaml.safe_load("""
3: a b c
2: a b c d
1: a b c f
#lang rosette/safe
(require rosette/lib/angelic rosette/lib/match)
; Circuit building block: NAND gates only
(struct nand (x y) #:transparent)
(define (interpret p)
(match p
[(nand x y) (not (and (interpret x) (interpret y)))]
[_ p]))
adamgreig /
Created October 9, 2018 23:31 — forked from tangrs/
Convert a memory dump/raw binary image into an ELF file
# Convert a raw binary image into an ELF file suitable for loading into a disassembler
cat > raw$$.ld <<EOF
echo " . = $3;" >> raw$$.ld
import traceback
from binaryninja import (BinaryView, Architecture, SegmentFlag, log_error,
get_address_input, log_info, SectionSemantics)
offset = 0x08000000
entry_addr = 0x080001c0
class FwImgView(BinaryView):
adamgreig /
Created December 14, 2017 05:56
AXI3 read-only slave in migen for Cyclone V SoC
from migen import Module, Signal, FSM, If, NextState, NextValue
class AXI3SlaveReader(Module):
AXI3 read-only slave.
Input signals are from the AXI3 master AR and R ports.
`regfile` is an Array which is indexed to respond to reads.