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View multinpnr.py
#!/usr/bin/env python3
import re
import sys
import time
import subprocess
import multiprocessing
import termplotlib as tpl
import numpy as np
View cl.py
import subprocess
import nmigen as nm
from nmigen.build import Resource, Pins, PinsN, Attrs, Clock, Subsignal
from nmigen.vendor.lattice_ecp5 import LatticeECP5Platform
class UART(nm.Elaboratable):
def __init__(self, data, divider=217, n=8):
assert divider >= 1
self.valid = nm.Signal()
View lfe5u-25f-pins.py
"""
Takes an ecpunpack output .config file and a iodb.json and works out attributes
set for each package pin as best it can.
LFE5U-25F-xBG256 only.
"""
import re
import sys
import json
View screenshot_sdg.py
import io
import sys
import time
import socket
import struct
from PIL import Image
if len(sys.argv) != 3:
print("Usage: screenshot.py <IP address> <filename>")
@adamgreig
adamgreig / check.py
Created May 17, 2020
check stm32f3 patches for correct exti values
View check.py
import sys
import os.path
import yaml
MAP = yaml.safe_load("""
f301:
3: a b c
2: a b c d
1: a b c f
View nand.rkt
#lang rosette/safe
(require rosette/lib/angelic rosette/lib/match)
; Circuit building block: NAND gates only
(struct nand (x y) #:transparent)
(define (interpret p)
(match p
[(nand x y) (not (and (interpret x) (interpret y)))]
[_ p]))
@adamgreig
adamgreig / bin2elf.sh
Created Oct 9, 2018 — forked from tangrs/bin2elf.sh
Convert a memory dump/raw binary image into an ELF file
View bin2elf.sh
#!/bin/sh
# Convert a raw binary image into an ELF file suitable for loading into a disassembler
cat > raw$$.ld <<EOF
SECTIONS
{
EOF
echo " . = $3;" >> raw$$.ld
View binja-fwimg.py
import traceback
from binaryninja import (BinaryView, Architecture, SegmentFlag, log_error,
get_address_input, log_info, SectionSemantics)
offset = 0x08000000
entry_addr = 0x080001c0
class FwImgView(BinaryView):
@adamgreig
adamgreig / axi3.py
Created Dec 14, 2017
AXI3 read-only slave in migen for Cyclone V SoC
View axi3.py
from migen import Module, Signal, FSM, If, NextState, NextValue
class AXI3SlaveReader(Module):
"""
AXI3 read-only slave.
Input signals are from the AXI3 master AR and R ports.
`regfile` is an Array which is indexed to respond to reads.
View psudmm.py
import sys
import time
import socket
import datetime
import numpy as np
import matplotlib.pyplot as plt
if len(sys.argv) != 4:
print("Usage: psudmm.py <Channel> <Max Voltage> <Voltage Step>")
sys.exit(1)