newhouseb

# This is an nmigen delay line for ECP5 FPGAs using the open source toolchain. It strings together a series of
# manually placed carry chains into a "thermometer." It returns a signal that's (length) long that represents
# the chain "snapshotted" at the primary clock domain (using the flip flops colocated in the slice).
#
# This can be used in a Time to Digital Converter (i.e. to measure the time between to events) or in
# an ADC by comparing (with LVDS) a signal to a reference signal.
#
# Note that the bit precision (read: delay per carry element) varies as a function of temperature. On 
# a LFE5U-25F-8MG285C, I've measure delay times of approximately 43ps on average. Due to assorted reasons,
# the delay time will vary between bits and due to variations in routing (even when manually places), you might 

smunaut

UP5k SG48:

ID	Use	SB_IO_GB	SB_GB	Special
		x/y/z (pin)	x/y	x/y type
0	Clk / Reset	19/ 0/1 (20)	13/ 0
1	Clk / CE	6/ 0/1 (44)	13/31
2	Clk / Reset	13/31/0 (37)	19/31	12/31 PLL_B
3	Clk / CE		6/31

jFransham

Achieving warp speed with Rust

Contents:

• Number one optimization tip: don't
• Never optimize blindly
• Don't bother optimizing one-time costs
• Improve your algorithms
• CPU architecture primer
• Keep as much as possible in cache
• Keep as much as possible in registers

audreyfeldroy

• Update HISTORY.md
• Commit the changes:

git add HISTORY.md
git commit -m "Changelog for upcoming release 0.1.1."

• Update version number (can also be minor or major)

bumpversion patch