check stm32f3 patches for correct exti values

check.py

import sys
import os.path
import yaml


MAP = yaml.safe_load("""
f301:
    3: a b c
    2: a b c d
    1: a b c f
    0: a b c f
    7: a b c
    6: a b c
    5: a b c
    4: a b c
    11: a b c
    10: a b c
    9: a b c
    8: a b c
    15: a b c
    14: a b c
    13: a b c
    12: a b c
f302:
    3: a b c d e
    2: a b c d e f
    1: a b c d e f
    0: a b c d e f
    7: a b c d e
    6: a b c d e f
    5: a b c d e f
    4: a b c d e f
    11: a b c d e
    10: a b c d e f
    9: a b c d e f
    8: a b c d e
    15: a b c d e
    14: a b c d e
    13: a b c d e
    12: a b c d e
f303:
    3: a b c d e f g
    2: a b c d e f g h
    1: a b c d e f g h
    0: a b c d e f g h
    7: a b c d e f g
    6: a b c d e f g
    5: a b c d e f g
    4: a b c d e f g
    11: a b c d e f g
    10: a b c d e f g
    9: a b c d e f g
    8: a b c d e f g
    15: a b c d e f g
    14: a b c d e f g
    13: a b c d e f g
    12: a b c d e f g
f37x:
    0: a b c d e f
    1: a b c d e f
    2: a b c d e f
    3: a b c d e
    4: a b c d e f
    5: a b c d e
    6: a b c d e f
    7: a b c d e f
    8: a b c d e
    9: a b c d e f
    10: a b c d e f
    11: a c d e
    12: a c d e
    13: a c d e
    14: a b c d e
    15: a b c d e
f3x4:
    3: a b c d e
    2: a b c d e f
    1: a b c d e f
    0: a b c d e f
    7: a b c d e
    6: a b c d e f
    5: a b c d e f
    4: a b c d e f
    11: a b c d e
    10: a b c d e f
    9: a b c d e f
    8: a b c d e
    15: a b c d e
    14: a b c d e
    13: a b c d e
    12: a b c d e
""")


def check(fname):
    with open(fname) as f:
        syscfg = yaml.safe_load(f)['SYSCFG']
    part = os.path.basename(fname)[7:11]
    if part not in MAP:
        print(f"No map found for {part}, skipping")
        return
    fmap = MAP[part]
    for reg in syscfg:
        if reg.startswith("EXTICR"):
            for field in syscfg[reg]:
                print(f"Checking {fname} {reg} {field}")
                patch_ports = set()
                for variant, (val, desc) in syscfg[reg][field].items():
                    assert variant[0] == "P"
                    port = variant[1]
                    patch_ports.add(port.lower())
                    port_int = ord(port) - ord('A')
                    assert port_int == val, variant
                    words = desc.split(" ")
                    assert variant == words[1], variant
                    assert words[8] == field, variant
                exti_num = int(field[4:].strip())
                map_ports = [port.strip() for port in fmap[exti_num].split(" ")]
                assert set(map_ports) == patch_ports, field


if __name__ == "__main__":
    for fname in sys.argv[1:]:
        check(fname)