4*8 RAM

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Ram_4_8 is
    Port ( clk : in std_logic;
           r_w : in std_logic;
           Addr: in integer range 0 to 3 ;
           Data_in : in std_logic_vector(7 downto 0);
           Data_out : out std_logic_vector(7 downto 0));
end Ram_4_8;

architecture Behavioral of Ram_4_8 is
type array_type is array (0 to 3) of std_logic_vector(7 downto 0);
signal matrix:array_type;
begin
process(clk,r_w)
begin
if clk'event and clk='1' then
if r_w='0'then
Data_out<=matrix(Addr);
else
matrix(Addr)<=Data_in;
Data_out<=(others =>'Z');
end if;
end if;
end process;
end Behavioral;

Generic RAM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Ram_4_8 is
    Port ( clk : in std_logic;
           r_w : in std_logic;
           Addr: in integer range 0 to 3 ;
           Data_in : in std_logic_vector(7 downto 0);
           Data_out : out std_logic_vector(7 downto 0));
end Ram_4_8;

architecture Behavioral of Ram_4_8 is
type array_type is array (0 to 3) of std_logic_vector(7 downto 0);
signal matrix:array_type;
begin
process(clk,r_w)
begin
if clk'event and clk='1' then
if r_w='0'then
Data_out<=matrix(Addr);
else
matrix(Addr)<=Data_in;
Data_out<=(others =>'Z');
end if;
end if;
end process;
end Behavioral;