main.v

module crc32 (
  input wire clk,
  input wire reset,
  input wire [7:0] data_in,
  output wire [7:0] data_out,
  output wire crc_valid
);

  reg [31:0] crc_reg;

  parameter POLYNOMIAL = 32'h04C11DB7;

  always @(posedge clk or posedge reset)
    if (reset) begin
      crc_reg <= 32'hFFFFFFFF;
      data_out <= 8'b0;
      crc_valid <= 1'b0;
    end
    else begin
      // shift the 8 bits into the crc_reg
      crc_reg <= {crc_reg[23:0], data_in};

      crc_reg <= {crc_reg[31], crc_reg[31:1]} ^ (crc_reg[0] ? POLYNOMIAL : 32'b0);

      data_out <= crc_reg[31:24];


      crc_valid <= (crc_reg == 32'b0);
    end
endmodule