bcd_counter.v

module bcd_counter (
	input clk,
	output reg [3:0] digit1,
	output reg [3:0] digit2,
	output reg [3:0] digit3
);

	always @(posedge clk) begin
		// wrap around logic
		if (digit1 == 4'd2 && digit2 == 4'd5 && digit3 == 4'd5) begin
			digit1 <= 4'd0;
			digit2 <= 4'd0;
			digit3 <= 4'd0;
		end else if (digit3 == 4'd9) begin
			digit3 <= 4'd0;
			if (digit2 == 4'd9) begin
				digit2 <= 4'd0;
				digit1 <= 4'd1 + digit1;
			end else begin
				digit2 <= 4'd1 + digit2;
			end
		end

		else
		begin
			// increment digit 3 normally
			digit3 <= 4'd1 + digit3;
		end


	end
endmodule