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@aki-lua87
Last active August 29, 2015 14:06
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module led_input(GPIO,hled1,CLK);
input GPIO,CLK;
output [7:0] hled1;
reg [127:0] rand;
reg [6:0] offset;
reg [25:0] count = 0;
reg [10:0] input_max = 0;
reg [4:0] head = 0;
reg [16:0] input_count = 0;
reg [16:0] bit_error_count = 0;
reg [6:0] bit_error_rate = 0;
reg input_scan,debug_num;
integer n = 0;
/* mk retu create */
function[127:0] randc;
input [6:0] rand;
integer i;
begin
randc[6:0] = rand;
i = 7;
while(i < 127) begin
randc[i] = randc[i-7]^randc[i-1];
i = i+1;
end
randc[127] = 0;
end
endfunction
always @(posedge CLK) begin
if(count == 4) count <= 0; /* 1250 = 25us */
else count <= count +1;
end
assign enable = (count == 0)?1:0;
always @(posedge CLK) begin
if(enable == 1) begin
rand = randc(7'b1111111);
offset = offset +1; end
end
/* ********kokomade********* */
/* hikaku */
always @(posedge CLK) begin
if(enable == 1) begin
if(input_max < 1001) begin
if(head != 7) begin
if(GPIO == 1) begin
head = head + 1;
n = n + 1; end
else begin
head = 0;
n = 0; end
end
else begin
if(GPIO == rand[n]) begin
n = n + 1;
input_count = input_count + 1; end
else begin
n = n + 1;
input_count = input_count + 1;
bit_error_count = bit_error_count + 1; end
if(n == 128) begin n = 0; end
bit_error_rate = 100*bit_error_count/input_count;
input_max = input_max + 1;
end
end
end
end
always @(posedge CLK) begin
if(enable == 1) begin
input_scan = GPIO;
end
if(input_max == 1000) begin
debug_num = 1;
end
end
/* output */
assign hled1[5:0] = bit_error_count[5:0];
assign hled1[6] = debug_num; /* debug yo */
assign hled1[7] = input_scan; /* debug yo sono2 */
endmodule
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