proposed DT snippet for proper multi-parent bus gates clock

gistfile1.txt

		bus_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-h3-bus-gates-clk", "allwinner,sunxi-bus-gates-clk";
			reg = <0x01c20060 0x14>;
			ahb1_parent {
			  clocks = <&ahb1>;
			  clock-indices = <5>, <6>, <8>, ....
			  clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", ...
			};
			apb1_parent {
			  clocks = <&apb1>;
			  clock-indices = <54>, <64>,
			                  <65>, <69>, <72>, ...
			  clock-output-names = "apb1_spdif", "apb1_pio", "apb1_ths", ...
			};
			ahb2_parent {
			    ....
			};
		};