Created
January 26, 2016 14:55
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working .dts for Pine64
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| /dts-v1/; | |
| /memreserve/ 0x0000000045000000 0x0000000000200000; | |
| /memreserve/ 0x0000000041010000 0x0000000000010800; | |
| /memreserve/ 0x0000000040100000 0x0000000000006000; | |
| / { | |
| model = "Pine64+"; | |
| compatible = "pine64,pine64_plus", "allwinner,a64"; | |
| interrupt-parent = <0x1>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| rtc { | |
| compatible = "allwinner,sun6i-a31-rtc"; | |
| reg = <0x1f00000 0x54>; | |
| interrupts = <0x0 0x28 0x4 0x0 0x29 0x4>; | |
| }; | |
| pinctrl { | |
| linux,phandle = <0x8>; | |
| phandle = <0x8>; | |
| compatible = "allwinner,a64-pinctrl"; | |
| reg = <0x1c20800 0x400>; | |
| interrupts = <0x0 0xb 0x4 0x0 0x11 0x4 0x0 0x15 0x4>; | |
| clocks = <0x13 0x45>; | |
| gpio-controller; | |
| interrupt-controller; | |
| #interrupt-cells = <0x3>; | |
| #gpio-cells = <0x3>; | |
| mmc0_cd_pin { | |
| phandle = <0x4>; | |
| linux,phandle = <0x4>; | |
| allwinner,pull = <0x1>; | |
| allwinner,drive = <0x0>; | |
| allwinner,function = "gpio_in"; | |
| allwinner,pins = "PF6"; | |
| }; | |
| mmc0 { | |
| phandle = <0x3>; | |
| linux,phandle = <0x3>; | |
| allwinner,pull = <0x0>; | |
| allwinner,drive = <0x2>; | |
| allwinner,function = "mmc0"; | |
| allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; | |
| }; | |
| uart0 { | |
| allwinner,pull = <0x0>; | |
| allwinner,drive = <0x0>; | |
| allwinner,function = "uart0"; | |
| allwinner,pins = "PB8", "PB9"; | |
| }; | |
| }; | |
| reg_vcc3v3 { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vcc3v3"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| linux,phandle = <0x5>; | |
| phandle = <0x5>; | |
| }; | |
| mmc0 { | |
| compatible = "allwinner,sun5i-a13-mmc"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0x1c0f000 0x1000>; | |
| interrupts = <0x0 0x3c 0x4>; | |
| bus-width = <0x4>; | |
| clock-names = "ahb", "mmc", "output", "sample"; | |
| clocks = <0x13 0x8 0x7 0x0 0x7 0x1 0x7 0x2>; | |
| vmmc-supply = <0x5>; | |
| cd-inverted; | |
| cd-gpios = <0x8 0x5 0x6 0x0>; | |
| }; | |
| aliases { | |
| serial0 = "/uart0"; | |
| }; | |
| uart0 { | |
| compatible = "snps,dw-apb-uart"; | |
| reg = <0x1c28000 0x400>; | |
| interrupts = <0x0 0x0 0x4>; | |
| clocks = <0x2>; | |
| reg-shift = <0x2>; | |
| reg-io-width = <0x4>; | |
| }; | |
| clocks { | |
| ranges; | |
| #size-cells = <0x1>; | |
| #address-cells = <0x1>; | |
| mmc_clk { | |
| #clock-cells = <0x1>; | |
| compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| reg = <0x1c20088 0x4>; | |
| clocks = <0x2 0xa 0x0 0xb>; | |
| clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; | |
| phandle = <0x7>; | |
| linux,phandle = <0x7>; | |
| }; | |
| bus_gates { | |
| clock-output-names = "bus_mmc0", "bus_pio"; | |
| clock-indices = <0x8 0x45>; | |
| clock-names = "ahb1", "ahb2", "apb1", "apb2"; | |
| clocks = <0x9 0xf 0x11 0x12>; | |
| reg = <0x1c20060 0x14>; | |
| compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
| #clock-cells = <0x1>; | |
| phandle = <0x13>; | |
| linux,phandle = <0x13>; | |
| }; | |
| apb2_clk { | |
| clock-output-names = "apb2"; | |
| clocks = <0xc 0x2 0xa 0x0 0xa 0x0>; | |
| reg = <0x1c20058 0x4>; | |
| compatible = "allwinner,sun4i-a10-apb1-clk"; | |
| #clock-cells = <0x0>; | |
| phandle = <0x12>; | |
| linux,phandle = <0x12>; | |
| }; | |
| apb1_clk { | |
| clock-output-names = "apb1"; | |
| clocks = <0x9>; | |
| reg = <0x1c20054 0x4>; | |
| compatible = "allwinner,sun4i-a10-apb0-clk"; | |
| #clock-cells = <0x0>; | |
| phandle = <0x11>; | |
| linux,phandle = <0x11>; | |
| }; | |
| ahb2_clk { | |
| clock-output-names = "ahb2"; | |
| clocks = <0x9 0x10>; | |
| reg = <0x1c2005c 0x4>; | |
| compatible = "allwinner,sun8i-h3-ahb2-clk"; | |
| #clock-cells = <0x0>; | |
| phandle = <0xf>; | |
| linux,phandle = <0xf>; | |
| }; | |
| ahb1_clk { | |
| clock-output-names = "ahb1"; | |
| clocks = <0xc 0x2 0x6 0xa 0x0>; | |
| reg = <0x1c20054 0x4>; | |
| compatible = "allwinner,sun6i-a31-ahb1-clk"; | |
| #clock-cells = <0x0>; | |
| phandle = <0x9>; | |
| linux,phandle = <0x9>; | |
| }; | |
| axi_clk { | |
| clock-output-names = "axi"; | |
| clocks = <0xe>; | |
| reg = <0x1c20050 0x4>; | |
| compatible = "allwinner,sun4i-a10-cpu-clk"; | |
| #clock-cells = <0x0>; | |
| phandle = <0x6>; | |
| linux,phandle = <0x6>; | |
| }; | |
| cpu_clk { | |
| clock-output-names = "cpu"; | |
| clocks = <0xc 0x2 0xd 0xd>; | |
| reg = <0x1c20050 0x4>; | |
| compatible = "allwinner,sun4i-a10-cpu-clk"; | |
| #clock-cells = <0x0>; | |
| phandle = <0xe>; | |
| linux,phandle = <0xe>; | |
| }; | |
| pll8 { | |
| clock-frequency = <0x1>; | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-output-names = "pll8"; | |
| phandle = <0xb>; | |
| linux,phandle = <0xb>; | |
| }; | |
| pll6d2 { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0xa 0x0>; | |
| clock-output-names = "pll6d2"; | |
| phandle = <0x10>; | |
| linux,phandle = <0x10>; | |
| }; | |
| pll6 { | |
| #clock-cells = <0x1>; | |
| compatible = "allwinner,sun6i-a31-pll6-clk"; | |
| reg = <0x1c20028 0x4>; | |
| clocks = <0x2>; | |
| clock-output-names = "pll6", "pll6x2"; | |
| phandle = <0xa>; | |
| linux,phandle = <0xa>; | |
| }; | |
| pll1 { | |
| #clock-cells = <0x0>; | |
| compatible = "allwinner,sun8i-a23-pll1-clk"; | |
| reg = <0x1c20000 0x4>; | |
| clocks = <0x2>; | |
| clock-output-names = "pll1"; | |
| phandle = <0xd>; | |
| linux,phandle = <0xd>; | |
| }; | |
| osc32k_clk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x8000>; | |
| clock-output-names = "osc32k"; | |
| phandle = <0xc>; | |
| linux,phandle = <0xc>; | |
| }; | |
| osc24M_clk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x16e3600>; | |
| clock-output-names = "osc24M"; | |
| phandle = <0x2>; | |
| linux,phandle = <0x2>; | |
| }; | |
| }; | |
| psci { | |
| method = "smc"; | |
| compatible = "arm,psci-0.2"; | |
| }; | |
| chosen { | |
| bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init"; | |
| linux,initrd-start = <0x0 0x0>; | |
| linux,initrd-end = <0x0 0x0>; | |
| }; | |
| cpus { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x0 0x0>; | |
| enable-method = "psci"; | |
| cpufreq_tbl = <0x75300 0x927c0 0xafc80 0xc7380 0xf6180 0x10d880 0x119400 0x124f80 0x148200>; | |
| clock-latency = <0x1e8480>; | |
| clock-frequency = <0x3c14dc00>; | |
| cpu-idle-states = <0x90 0x91 0x92>; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x0 0x1>; | |
| enable-method = "psci"; | |
| clock-frequency = <0x3c14dc00>; | |
| cpu-idle-states = <0x90 0x91 0x92>; | |
| }; | |
| cpu@2 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x0 0x2>; | |
| enable-method = "psci"; | |
| clock-frequency = <0x3c14dc00>; | |
| cpu-idle-states = <0x90 0x91 0x92>; | |
| }; | |
| cpu@3 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x0 0x3>; | |
| enable-method = "psci"; | |
| clock-frequency = <0x3c14dc00>; | |
| cpu-idle-states = <0x90 0x91 0x92>; | |
| }; | |
| }; | |
| memory@40000000 { | |
| device_type = "memory"; | |
| reg = <0x41000000 0x3f000000>; | |
| }; | |
| interrupt-controller@1c81000 { | |
| compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | |
| #interrupt-cells = <0x3>; | |
| #address-cells = <0x0>; | |
| device_type = "gic"; | |
| interrupt-controller; | |
| reg = <0x1c81000 0x1000 0x1c82000 0x2000 0x1c84000 0x2000 0x1c86000 0x2000>; | |
| interrupts = <0x1 0x9 0xf04>; | |
| linux,phandle = <0x1>; | |
| phandle = <0x1>; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <0x1 0xd 0xff01 0x1 0xe 0xff01 0x1 0xb 0xff01 0x1 0xa 0xff01>; | |
| clock-frequency = <0x16e3600>; | |
| }; | |
| uboot { | |
| }; | |
| }; |
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