R40 dual rank hack

r40_dram_dual_rank.diff

diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index d0600011ffa..5dcafa21bc9 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -388,8 +388,9 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
 {
        struct sunxi_mctl_com_reg * const mctl_com =
                        (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+       u32 cr_val;
 
-       writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED |
+       cr_val = MCTL_CR_BL8 | MCTL_CR_INTERLEAVED |
 #if defined CONFIG_SUNXI_DRAM_DDR3
               MCTL_CR_DDR3 | MCTL_CR_2T |
 #elif defined CONFIG_SUNXI_DRAM_DDR2
@@ -403,14 +404,16 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
               MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
               (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
               MCTL_CR_PAGE_SIZE(para->page_size) |
-              MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
+              MCTL_CR_ROW_BITS(para->row_bits);
+
+       writel(cr_val, &mctl_com->cr);
 
        if (socid == SOCID_R40) {
                if (para->dual_rank)
-                       panic("Dual rank memory not supported\n");
-
-               /* Mux pin to A15 address line for single rank memory. */
-               setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
+                       writel(cr_val, &mctl_com->cr_r1);
+               else
+                       /* Mux pin to A15 address line for single rank memory. */
+                       setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
        }
 }