Created
July 9, 2016 17:42
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adding the PMU node to the A64 .dtsi
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | |
index 80b0a49..0a7865a 100644 | |
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | |
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | |
@@ -54,28 +54,28 @@ | |
#address-cells = <1>; | |
#size-cells = <0>; | |
- cpu@0 { | |
+ cpu0: cpu@0 { | |
compatible = "arm,cortex-a53", "arm,armv8"; | |
device_type = "cpu"; | |
reg = <0>; | |
enable-method = "psci"; | |
}; | |
- cpu@1 { | |
+ cpu1: cpu@1 { | |
compatible = "arm,cortex-a53", "arm,armv8"; | |
device_type = "cpu"; | |
reg = <1>; | |
enable-method = "psci"; | |
}; | |
- cpu@2 { | |
+ cpu2: cpu@2 { | |
compatible = "arm,cortex-a53", "arm,armv8"; | |
device_type = "cpu"; | |
reg = <2>; | |
enable-method = "psci"; | |
}; | |
- cpu@3 { | |
+ cpu3: cpu@3 { | |
compatible = "arm,cortex-a53", "arm,armv8"; | |
device_type = "cpu"; | |
reg = <3>; | |
@@ -83,6 +83,18 @@ | |
}; | |
}; | |
+ pmu { | |
+ compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; | |
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, | |
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; | |
+ interrupt-affinity = <&cpu0>, | |
+ <&cpu1>, | |
+ <&cpu2>, | |
+ <&cpu3>; | |
+ }; | |
+ | |
psci { | |
compatible = "arm,psci-0.2"; | |
method = "smc"; |
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