UART Loopback for 12MHz clock

UARTLoopback12MHz.v

//
// Generated by Bluespec Compiler (build 3467c84)
//
// On Tue Feb 23 01:14:43 PST 2021
//
//
// Ports:
// Name                         I/O  size props
// tx                             O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// rx                             I     1 reg
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module UARTLoopback12MHz(CLK,
			 RST_N,

			 rx,

			 tx);
  input  CLK;
  input  RST_N;

  // action method rx
  input  rx;

  // value method tx
  output tx;

  // signals for module outputs
  wire tx;

  // inlined wires
  wire transceiver_rx_sampler_search_for_bit_edge_$whas,
       transceiver_ser_i_next$whas;

  // register rx_sync
  reg rx_sync;
  wire rx_sync$D_IN, rx_sync$EN;

  // register sample_strobe_
  reg sample_strobe_;
  wire sample_strobe_$D_IN, sample_strobe_$EN;

  // register sample_strobe__count
  reg [15 : 0] sample_strobe__count;
  wire [15 : 0] sample_strobe__count$D_IN;
  wire sample_strobe__count$EN;

  // register transceiver_des_o
  reg [8 : 0] transceiver_des_o;
  wire [8 : 0] transceiver_des_o$D_IN;
  wire transceiver_des_o$EN;

  // register transceiver_des_state
  reg [3 : 0] transceiver_des_state;
  wire [3 : 0] transceiver_des_state$D_IN;
  wire transceiver_des_state$EN;

  // register transceiver_rx_sampler_samples
  reg [7 : 0] transceiver_rx_sampler_samples;
  wire [7 : 0] transceiver_rx_sampler_samples$D_IN;
  wire transceiver_rx_sampler_samples$EN;

  // register transceiver_rx_strobe
  reg transceiver_rx_strobe;
  wire transceiver_rx_strobe$D_IN, transceiver_rx_strobe$EN;

  // register transceiver_rx_strobe_count
  reg [2 : 0] transceiver_rx_strobe_count;
  wire [2 : 0] transceiver_rx_strobe_count$D_IN;
  wire transceiver_rx_strobe_count$EN;

  // register transceiver_ser_i
  reg [8 : 0] transceiver_ser_i;
  wire [8 : 0] transceiver_ser_i$D_IN;
  wire transceiver_ser_i$EN;

  // register transceiver_ser_o
  reg transceiver_ser_o;
  wire transceiver_ser_o$D_IN, transceiver_ser_o$EN;

  // register transceiver_ser_state
  reg [3 : 0] transceiver_ser_state;
  reg [3 : 0] transceiver_ser_state$D_IN;
  wire transceiver_ser_state$EN;

  // register transceiver_tx_strobe_
  reg transceiver_tx_strobe_;
  wire transceiver_tx_strobe_$D_IN, transceiver_tx_strobe_$EN;

  // register transceiver_tx_strobe__count
  reg [2 : 0] transceiver_tx_strobe__count;
  wire [2 : 0] transceiver_tx_strobe__count$D_IN;
  wire transceiver_tx_strobe__count$EN;

  // ports of submodule transceiver_rx_sampler_q
  wire transceiver_rx_sampler_q$CLR,
       transceiver_rx_sampler_q$DEQ,
       transceiver_rx_sampler_q$D_IN,
       transceiver_rx_sampler_q$D_OUT,
       transceiver_rx_sampler_q$EMPTY_N,
       transceiver_rx_sampler_q$ENQ;

  // rule scheduling signals
  wire WILL_FIRE_RL_transceiver_rx_strobe_do_set;

  // inputs to muxes for submodule ports
  wire MUX_transceiver_rx_strobe_count$write_1__SEL_2;

  // remaining internal signals
  reg [7 : 0] CASE_transceiver_ser_state_0_IF_transceiver_se_ETC__q2;
  wire [16 : 0] _0_CONCAT_sample_strobe__count_PLUS_5041___d8;
  wire [8 : 0] transceiver_des_state_0_EQ_0_1_AND_NOT_transce_ETC___d116;
  wire [7 : 0] IF_transceiver_des_state_0_EQ_0_1_OR_transceiv_ETC___d113,
	       IF_transceiver_des_state_0_EQ_10_5_AND_NOT_tra_ETC___d112,
	       IF_transceiver_ser_i_next_whas__7_THEN_transce_ETC___d38,
	       transceiver_des_o_BITS_7_TO_0__q1;
  wire [3 : 0] IF_transceiver_ser_i_next_whas__7_OR_transceiv_ETC___d47,
	       _0_CONCAT_transceiver_rx_strobe_count_32_33_PLUS_1___d134,
	       _0_CONCAT_transceiver_tx_strobe__count_1_2_PLUS_1___d63;
  wire IF_transceiver_des_state_0_EQ_0_1_AND_transcei_ETC___d91,
       IF_transceiver_des_state_0_EQ_9_1_AND_transcei_ETC___d89,
       IF_transceiver_ser_state_5_EQ_0_6_THEN_transce_ETC___d27,
       IF_transceiver_ser_state_5_EQ_10_3_THEN_NOT_tr_ETC___d53;

  // value method tx
  assign tx = transceiver_ser_o ;

  // submodule transceiver_rx_sampler_q
  FIFO1 #(.width(32'd1),
	  .guarded(32'd1)) transceiver_rx_sampler_q(.RST(RST_N),
						    .CLK(CLK),
						    .D_IN(transceiver_rx_sampler_q$D_IN),
						    .ENQ(transceiver_rx_sampler_q$ENQ),
						    .DEQ(transceiver_rx_sampler_q$DEQ),
						    .CLR(transceiver_rx_sampler_q$CLR),
						    .D_OUT(transceiver_rx_sampler_q$D_OUT),
						    .FULL_N(),
						    .EMPTY_N(transceiver_rx_sampler_q$EMPTY_N));

  // rule RL_transceiver_rx_strobe_do_set
  assign WILL_FIRE_RL_transceiver_rx_strobe_do_set =
	     sample_strobe_ && transceiver_rx_sampler_samples[4:0] == 5'd1 ;

  // inputs to muxes for submodule ports
  assign MUX_transceiver_rx_strobe_count$write_1__SEL_2 =
	     sample_strobe_ && !WILL_FIRE_RL_transceiver_rx_strobe_do_set ;

  // inlined wires
  assign transceiver_ser_i_next$whas =
	     !transceiver_ser_i[8] && transceiver_des_o[8] &&
	     (transceiver_des_state == 4'd10 ||
	      transceiver_des_state == 4'd0) ;
  assign transceiver_rx_sampler_search_for_bit_edge_$whas =
	     transceiver_des_state == 4'd0 || transceiver_des_state == 4'd10 ;

  // register rx_sync
  assign rx_sync$D_IN = rx ;
  assign rx_sync$EN = 1'd1 ;

  // register sample_strobe_
  assign sample_strobe_$D_IN =
	     _0_CONCAT_sample_strobe__count_PLUS_5041___d8[16] ;
  assign sample_strobe_$EN = 1'd1 ;

  // register sample_strobe__count
  assign sample_strobe__count$D_IN =
	     _0_CONCAT_sample_strobe__count_PLUS_5041___d8[15:0] ;
  assign sample_strobe__count$EN = 1'b1 ;

  // register transceiver_des_o
  assign transceiver_des_o$D_IN =
	     transceiver_rx_sampler_q$EMPTY_N ?
	       transceiver_des_state_0_EQ_0_1_AND_NOT_transce_ETC___d116 :
	       { !transceiver_ser_i_next$whas && transceiver_des_o[8],
		 transceiver_des_o[7:0] } ;
  assign transceiver_des_o$EN = 1'd1 ;

  // register transceiver_des_state
  assign transceiver_des_state$D_IN =
	     (transceiver_des_state == 4'd0 &&
	      !transceiver_rx_sampler_q$D_OUT) ?
	       4'd1 :
	       ((transceiver_des_state == 4'd0 &&
		 transceiver_rx_sampler_q$D_OUT ||
		 transceiver_des_state == 4'd9 &&
		 !transceiver_rx_sampler_q$D_OUT) ?
		  4'd0 :
		  ((transceiver_des_state == 4'd9 &&
		    transceiver_rx_sampler_q$D_OUT) ?
		     4'd10 :
		     ((transceiver_des_state == 4'd10 &&
		       !transceiver_rx_sampler_q$D_OUT) ?
			4'd1 :
			((transceiver_des_state == 4'd10) ?
			   4'd0 :
			   transceiver_des_state + 4'd1)))) ;
  assign transceiver_des_state$EN = transceiver_rx_sampler_q$EMPTY_N ;

  // register transceiver_rx_sampler_samples
  assign transceiver_rx_sampler_samples$D_IN =
	     { rx_sync, transceiver_rx_sampler_samples[7:1] } ;
  assign transceiver_rx_sampler_samples$EN = sample_strobe_ ;

  // register transceiver_rx_strobe
  assign transceiver_rx_strobe$D_IN =
	     MUX_transceiver_rx_strobe_count$write_1__SEL_2 &&
	     _0_CONCAT_transceiver_rx_strobe_count_32_33_PLUS_1___d134[3] ;
  assign transceiver_rx_strobe$EN = 1'd1 ;

  // register transceiver_rx_strobe_count
  assign transceiver_rx_strobe_count$D_IN =
	     WILL_FIRE_RL_transceiver_rx_strobe_do_set ?
	       3'd1 :
	       _0_CONCAT_transceiver_rx_strobe_count_32_33_PLUS_1___d134[2:0] ;
  assign transceiver_rx_strobe_count$EN =
	     WILL_FIRE_RL_transceiver_rx_strobe_do_set ||
	     sample_strobe_ && !WILL_FIRE_RL_transceiver_rx_strobe_do_set ;

  // register transceiver_ser_i
  assign transceiver_ser_i$D_IN =
	     transceiver_tx_strobe_ ?
	       { IF_transceiver_ser_state_5_EQ_0_6_THEN_transce_ETC___d27,
		 CASE_transceiver_ser_state_0_IF_transceiver_se_ETC__q2 } :
	       { transceiver_ser_i_next$whas || transceiver_ser_i[8],
		 IF_transceiver_ser_i_next_whas__7_THEN_transce_ETC___d38 } ;
  assign transceiver_ser_i$EN = 1'd1 ;

  // register transceiver_ser_o
  assign transceiver_ser_o$D_IN =
	     (transceiver_ser_state == 4'd0) ?
	       !transceiver_ser_i_next$whas && !transceiver_ser_i[8] :
	       transceiver_ser_state == 4'd9 ||
	       IF_transceiver_ser_state_5_EQ_10_3_THEN_NOT_tr_ETC___d53 ;
  assign transceiver_ser_o$EN = transceiver_tx_strobe_ ;

  // register transceiver_ser_state
  always@(transceiver_ser_state or
	  IF_transceiver_ser_i_next_whas__7_OR_transceiv_ETC___d47)
  begin
    case (transceiver_ser_state)
      4'd0, 4'd10:
	  transceiver_ser_state$D_IN =
	      IF_transceiver_ser_i_next_whas__7_OR_transceiv_ETC___d47;
      4'd9: transceiver_ser_state$D_IN = 4'd10;
      default: transceiver_ser_state$D_IN = transceiver_ser_state + 4'd1;
    endcase
  end
  assign transceiver_ser_state$EN = transceiver_tx_strobe_ ;

  // register transceiver_tx_strobe_
  assign transceiver_tx_strobe_$D_IN =
	     sample_strobe_ &&
	     _0_CONCAT_transceiver_tx_strobe__count_1_2_PLUS_1___d63[3] ;
  assign transceiver_tx_strobe_$EN = 1'd1 ;

  // register transceiver_tx_strobe__count
  assign transceiver_tx_strobe__count$D_IN =
	     _0_CONCAT_transceiver_tx_strobe__count_1_2_PLUS_1___d63[2:0] ;
  assign transceiver_tx_strobe__count$EN = sample_strobe_ ;

  // submodule transceiver_rx_sampler_q
  assign transceiver_rx_sampler_q$D_IN = transceiver_rx_sampler_samples[4] ;
  assign transceiver_rx_sampler_q$ENQ =
	     1'b1 &&
	     (transceiver_rx_sampler_search_for_bit_edge_$whas &&
	      WILL_FIRE_RL_transceiver_rx_strobe_do_set ||
	      !transceiver_rx_sampler_search_for_bit_edge_$whas &&
	      transceiver_rx_strobe) ;
  assign transceiver_rx_sampler_q$DEQ = transceiver_rx_sampler_q$EMPTY_N ;
  assign transceiver_rx_sampler_q$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_transceiver_des_state_0_EQ_0_1_AND_transcei_ETC___d91 =
	     (transceiver_des_state == 4'd0 &&
	      transceiver_rx_sampler_q$D_OUT) ?
	       !transceiver_ser_i_next$whas && transceiver_des_o[8] :
	       (transceiver_des_state != 4'd9 ||
		transceiver_rx_sampler_q$D_OUT) &&
	       IF_transceiver_des_state_0_EQ_9_1_AND_transcei_ETC___d89 ;
  assign IF_transceiver_des_state_0_EQ_0_1_OR_transceiv_ETC___d113 =
	     ((transceiver_des_state == 4'd0 ||
	       transceiver_des_state == 4'd9) &&
	      transceiver_rx_sampler_q$D_OUT) ?
	       transceiver_des_o[7:0] :
	       IF_transceiver_des_state_0_EQ_10_5_AND_NOT_tra_ETC___d112 ;
  assign IF_transceiver_des_state_0_EQ_10_5_AND_NOT_tra_ETC___d112 =
	     (transceiver_des_state == 4'd10 &&
	      !transceiver_rx_sampler_q$D_OUT) ?
	       8'd0 :
	       ((transceiver_des_state == 4'd10 &&
		 transceiver_rx_sampler_q$D_OUT) ?
		  transceiver_des_o[7:0] :
		  { transceiver_rx_sampler_q$D_OUT,
		    transceiver_des_o_BITS_7_TO_0__q1[7:1] }) ;
  assign IF_transceiver_des_state_0_EQ_9_1_AND_transcei_ETC___d89 =
	     (transceiver_des_state == 4'd9 &&
	      transceiver_rx_sampler_q$D_OUT) ?
	       !transceiver_ser_i_next$whas && transceiver_des_o[8] :
	       transceiver_des_state != 4'd10 ||
	       !transceiver_rx_sampler_q$D_OUT ||
	       !transceiver_ser_i_next$whas && transceiver_des_o[8] ;
  assign IF_transceiver_ser_i_next_whas__7_OR_transceiv_ETC___d47 =
	     (transceiver_ser_i_next$whas || transceiver_ser_i[8]) ?
	       4'd1 :
	       4'd0 ;
  assign IF_transceiver_ser_i_next_whas__7_THEN_transce_ETC___d38 =
	     transceiver_ser_i_next$whas ?
	       transceiver_des_o[7:0] :
	       transceiver_ser_i[7:0] ;
  assign IF_transceiver_ser_state_5_EQ_0_6_THEN_transce_ETC___d27 =
	     (transceiver_ser_state == 4'd0) ?
	       transceiver_ser_i_next$whas || transceiver_ser_i[8] :
	       transceiver_ser_state != 4'd9 &&
	       (transceiver_ser_state != 4'd10 ||
		transceiver_ser_i_next$whas ||
		transceiver_ser_i[8]) ;
  assign IF_transceiver_ser_state_5_EQ_10_3_THEN_NOT_tr_ETC___d53 =
	     (transceiver_ser_state == 4'd10) ?
	       !transceiver_ser_i_next$whas && !transceiver_ser_i[8] :
	       IF_transceiver_ser_i_next_whas__7_THEN_transce_ETC___d38[0] ;
  assign _0_CONCAT_sample_strobe__count_PLUS_5041___d8 =
	     { 1'd0, sample_strobe__count } + 17'd5041 ;
  assign _0_CONCAT_transceiver_rx_strobe_count_32_33_PLUS_1___d134 =
	     { 1'd0, transceiver_rx_strobe_count } + 4'd1 ;
  assign _0_CONCAT_transceiver_tx_strobe__count_1_2_PLUS_1___d63 =
	     { 1'd0, transceiver_tx_strobe__count } + 4'd1 ;
  assign transceiver_des_o_BITS_7_TO_0__q1 = transceiver_des_o[7:0] ;
  assign transceiver_des_state_0_EQ_0_1_AND_NOT_transce_ETC___d116 =
	     { transceiver_des_state == 4'd0 &&
	       !transceiver_rx_sampler_q$D_OUT ||
	       IF_transceiver_des_state_0_EQ_0_1_AND_transcei_ETC___d91,
	       (transceiver_des_state == 4'd0 &&
		!transceiver_rx_sampler_q$D_OUT) ?
		 8'd0 :
		 IF_transceiver_des_state_0_EQ_0_1_OR_transceiv_ETC___d113 } ;
  always@(transceiver_ser_state or
	  IF_transceiver_ser_i_next_whas__7_THEN_transce_ETC___d38)
  begin
    case (transceiver_ser_state)
      4'd0, 4'd10:
	  CASE_transceiver_ser_state_0_IF_transceiver_se_ETC__q2 =
	      IF_transceiver_ser_i_next_whas__7_THEN_transce_ETC___d38;
      default: CASE_transceiver_ser_state_0_IF_transceiver_se_ETC__q2 =
		   { 1'd0,
		     IF_transceiver_ser_i_next_whas__7_THEN_transce_ETC___d38[7:1] };
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (rx_sync$EN) rx_sync <= `BSV_ASSIGNMENT_DELAY rx_sync$D_IN;
  end

  always@(posedge CLK or `BSV_RESET_EDGE RST_N)
  if (RST_N == `BSV_RESET_VALUE)
    begin
      sample_strobe_ <= `BSV_ASSIGNMENT_DELAY 1'd0;
      sample_strobe__count <= `BSV_ASSIGNMENT_DELAY 16'd0;
      transceiver_des_o <= `BSV_ASSIGNMENT_DELAY 9'd170;
      transceiver_des_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
      transceiver_rx_sampler_samples <= `BSV_ASSIGNMENT_DELAY 8'd255;
      transceiver_rx_strobe <= `BSV_ASSIGNMENT_DELAY 1'd0;
      transceiver_rx_strobe_count <= `BSV_ASSIGNMENT_DELAY 3'd0;
      transceiver_ser_i <= `BSV_ASSIGNMENT_DELAY 9'd170;
      transceiver_ser_o <= `BSV_ASSIGNMENT_DELAY 1'd1;
      transceiver_ser_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
      transceiver_tx_strobe_ <= `BSV_ASSIGNMENT_DELAY 1'd0;
      transceiver_tx_strobe__count <= `BSV_ASSIGNMENT_DELAY 3'd0;
    end
  else
    begin
      if (sample_strobe_$EN)
	sample_strobe_ <= `BSV_ASSIGNMENT_DELAY sample_strobe_$D_IN;
      if (sample_strobe__count$EN)
	sample_strobe__count <= `BSV_ASSIGNMENT_DELAY
	    sample_strobe__count$D_IN;
      if (transceiver_des_o$EN)
	transceiver_des_o <= `BSV_ASSIGNMENT_DELAY transceiver_des_o$D_IN;
      if (transceiver_des_state$EN)
	transceiver_des_state <= `BSV_ASSIGNMENT_DELAY
	    transceiver_des_state$D_IN;
      if (transceiver_rx_sampler_samples$EN)
	transceiver_rx_sampler_samples <= `BSV_ASSIGNMENT_DELAY
	    transceiver_rx_sampler_samples$D_IN;
      if (transceiver_rx_strobe$EN)
	transceiver_rx_strobe <= `BSV_ASSIGNMENT_DELAY
	    transceiver_rx_strobe$D_IN;
      if (transceiver_rx_strobe_count$EN)
	transceiver_rx_strobe_count <= `BSV_ASSIGNMENT_DELAY
	    transceiver_rx_strobe_count$D_IN;
      if (transceiver_ser_i$EN)
	transceiver_ser_i <= `BSV_ASSIGNMENT_DELAY transceiver_ser_i$D_IN;
      if (transceiver_ser_o$EN)
	transceiver_ser_o <= `BSV_ASSIGNMENT_DELAY transceiver_ser_o$D_IN;
      if (transceiver_ser_state$EN)
	transceiver_ser_state <= `BSV_ASSIGNMENT_DELAY
	    transceiver_ser_state$D_IN;
      if (transceiver_tx_strobe_$EN)
	transceiver_tx_strobe_ <= `BSV_ASSIGNMENT_DELAY
	    transceiver_tx_strobe_$D_IN;
      if (transceiver_tx_strobe__count$EN)
	transceiver_tx_strobe__count <= `BSV_ASSIGNMENT_DELAY
	    transceiver_tx_strobe__count$D_IN;
    end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    rx_sync = 1'h0;
    sample_strobe_ = 1'h0;
    sample_strobe__count = 16'hAAAA;
    transceiver_des_o = 9'h0AA;
    transceiver_des_state = 4'hA;
    transceiver_rx_sampler_samples = 8'hAA;
    transceiver_rx_strobe = 1'h0;
    transceiver_rx_strobe_count = 3'h2;
    transceiver_ser_i = 9'h0AA;
    transceiver_ser_o = 1'h0;
    transceiver_ser_state = 4'hA;
    transceiver_tx_strobe_ = 1'h0;
    transceiver_tx_strobe__count = 3'h2;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkUARTLoopback12MHz


`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

`ifdef BSV_ASYNC_RESET
 `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
 `define BSV_ARESET_EDGE_META
`endif

`ifdef BSV_RESET_FIFO_HEAD
 `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
 `define BSV_ARESET_EDGE_HEAD
`endif

// Depth 1 FIFO
module FIFO1(CLK,
             RST,
             D_IN,
             ENQ,
             FULL_N,
             D_OUT,
             DEQ,
             EMPTY_N,
             CLR
             );

   parameter width = 1;
   parameter guarded = 1;
   input                  CLK;
   input                  RST;
   input [width - 1 : 0]  D_IN;
   input                  ENQ;
   input                  DEQ;
   input                  CLR ;

   output                 FULL_N;
   output [width - 1 : 0] D_OUT;
   output                 EMPTY_N;

   reg [width - 1 : 0]    D_OUT;
   reg                    empty_reg ;


   assign                 EMPTY_N = empty_reg ;


`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
   // synopsys translate_off
   initial
     begin
        D_OUT   = {((width + 1)/2) {2'b10}} ;
        empty_reg = 1'b0 ;
     end // initial begin
   // synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS


   assign FULL_N = !empty_reg;

   always@(posedge CLK `BSV_ARESET_EDGE_META)
     begin
        if (RST == `BSV_RESET_VALUE)
          begin
             empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
          end // if (RST == `BSV_RESET_VALUE)
        else
           begin
              if (CLR)
                begin
                   empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
                end // if (CLR)
              else if (ENQ)
                begin
                   empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
                end // if (ENQ)
              else if (DEQ)
                begin
                   empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
                end // if (DEQ)
           end // else: !if(RST == `BSV_RESET_VALUE)
     end // always@ (posedge CLK or `BSV_RESET_EDGE RST)

   always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
     begin
`ifdef BSV_RESET_FIFO_HEAD
        if (RST == `BSV_RESET_VALUE)
          begin
             D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
          end
        else
`endif
           begin
              if (ENQ)
                D_OUT     <= `BSV_ASSIGNMENT_DELAY D_IN;
           end // else: !if(RST == `BSV_RESET_VALUE)
     end // always@ (posedge CLK or `BSV_RESET_EDGE RST)

   // synopsys translate_off
   always@(posedge CLK)
     begin: error_checks
        reg deqerror, enqerror ;

        deqerror =  0;
        enqerror = 0;
        if (RST == ! `BSV_RESET_VALUE)
           begin
              if ( ! empty_reg && DEQ )
                begin
                   deqerror = 1 ;
                   $display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
                end
              if ( ! FULL_N && ENQ && (!DEQ || guarded) )
                begin
                   enqerror =  1 ;
                   $display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
                end
           end // if (RST == ! `BSV_RESET_VALUE)
     end
   // synopsys translate_on

endmodule