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Yosys synthesis comparison GateMate, Nexus, ECP5, XC7 for 8x22 instruction decoder
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Yosys GateMate (synth_gatemate -noiopad): | |
=== mkOpcodeDecoder === | |
Number of wires: 242 | |
Number of wire bits: 675 | |
Number of public wires: 15 | |
Number of public wire bits: 84 | |
Number of memories: 0 | |
Number of memory bits: 0 | |
Number of processes: 0 | |
Number of cells: 386 | |
CC_BUFG 1 | |
CC_DFF 22 | |
CC_LUT1 3 | |
CC_LUT2 87 | |
CC_LUT3 99 | |
CC_LUT4 148 | |
CC_MX4 24 | |
CC_MX8 2 | |
Yosys Nexus (synth_nexus -noiopad) | |
=== mkOpcodeDecoder === | |
Number of wires: 319 | |
Number of wire bits: 371 | |
Number of public wires: 319 | |
Number of public wire bits: 371 | |
Number of memories: 0 | |
Number of memory bits: 0 | |
Number of processes: 0 | |
Number of cells: 332 | |
FD1P3IX 14 | |
FD1P3JX 8 | |
INV 1 | |
LUT4 271 | |
VHI 1 | |
WIDEFN9 37 | |
Yosys ECP5 (synth_ecp5 -noiopad): | |
=== mkOpcodeDecoder === | |
Number of wires: 965 | |
Number of wire bits: 1404 | |
Number of public wires: 965 | |
Number of public wire bits: 1404 | |
Number of memories: 0 | |
Number of memory bits: 0 | |
Number of processes: 0 | |
Number of cells: 1114 | |
L6MUX21 160 | |
LUT4 671 | |
PFUMX 261 | |
TRELLIS_FF 22 | |
Yosys Xilinx XC7 (synth_xilinx -family xc7 -noiopad): | |
=== mkOpcodeDecoder === | |
Number of wires: 166 | |
Number of wire bits: 242 | |
Number of public wires: 11 | |
Number of public wire bits: 68 | |
Number of memories: 0 | |
Number of memory bits: 0 | |
Number of processes: 0 | |
Number of cells: 182 | |
BUFG 1 | |
FDRE 14 | |
FDSE 8 | |
LUT2 4 | |
LUT3 13 | |
LUT4 5 | |
LUT5 9 | |
LUT6 64 | |
MUXF7 43 | |
MUXF8 21 | |
Estimated number of LCs: 91 | |
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