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Build Coreboot for ARM Chromebook - C201 Veyron Speedy

These instructions will take you through the step by step process of building and flashing a custom build of the Coreboot ROM to a Chromebook C201.

This guide expects you to have a Chromebook C201, and another ARM computer with Ubuntu installed. Specifically I used the Odroid XU2. You may be able to do this on an Intel platform, using a cross compiler. See the sidenotes section for more information.

Setting up your Ubuntu

Install dependancies

Update your Ubuntu aptitude and install the dependancies we will need.

sudo apt update
sudo apt install git build-essential gnat flex bison libncurses5-dev wget zlib1g-dev git

Clone

Change into your ~/Documents directory and clone the coreboot git repository [1]

cd ~/Documents
git clone --recurse-submodules https://review.coreboot.org/coreboot.git
git submodule update --init --checkout
cd coreboot

Bugfixs

There are a few tweaks to the coreboot sourcecode we need to do to make this work. I have asked about this on the coreboot mailing list [2].

Add Depthcharge to the menuconfig

If you are using the interactive menuconfig command you will want to add Depthcharge as a payload [3][4] option.

  1. Open the ~/Documents/coreboot/payloads/Kconfig file for editing
  2. Find the line config PAYLOAD_ELF. It should be near the top of the file around line 21.
  3. Insert the following above it:
config PAYLOAD_DEPTHCHARGE
	bool "Depthcharge"
	help
	  Select this option if you want to set depthcharge as your primary
          payload.
  1. Save the file

Depthcharge won't build

When you run make you are going to get an error message, something like below:

Your branch is up-to-date with 'origin/master'.
Switched to a new branch 'coreboot'
Error: ~/Documents/coreboot/payloads/libpayload/configs/config.veyron_speedy is not present
Makefile:65: recipe for target '~/Documents/coreboot/payloads/external/depthcharge/depthcharge/build/lp_veyron_speedy' failed
make[1]: *** [~/Documents/coreboot/payloads/external/depthcharge/depthcharge/build/lp_veyron_speedy] Error 1
payloads/external/Makefile.inc:112: recipe for target 'payloads/external/depthcharge/depthcharge/build/depthcharge.elf' failed
make: *** [payloads/external/depthcharge/depthcharge/build/depthcharge.elf] Error 2

There is very little documentation about the depthcharge and coreboot marriage, so I'm not really sure why this happening. At a guess, I would say there was an attempt to merge all the veyron configs into one which might require a new variable which I just can't find. So I have no doubt there is a better (proper) solution to this, but I've battled this for over an hour and the best I can come up with for now is to just duplicate the veyron config file below:

cp payloads/libpayload/configs/config.veyron payloads/libpayload/configs/config.veyron_speedy

Build Cross Compiler

You will only need to do this stage once to setup your environment. This installs the cross compiler. It's probably not nessisary as we are actually on an ARM machine, but I haven't quite worked that out yet.

Note this will take a long time, for me 15 minutes. Also, you will need to run it again if you clone the coreboot repository again.

make crossgcc-arm CPUS=12

Configure

The make menuconfig command gives an interactive method of configuring your coreboot build [5].

make menuconfig

There are quite a few options [6] in there, some which may be quite confusing. Thankfully coreboot normally includes a copy of the config file on your Chromebook. I will write up a guide of how to extract this from your Chromebook later on, as I'm writing the flashing guide. In the meantime I have included a copy of the .config file that came with my ASUS c201 Chromebook. Lots of those variables have been renamed/moved so you'll have to do a bit of matching to work out what maps to what.

In the meantime, at a minimum, the options you will want to change are:

Setting location value
Mainboard -> Mainboard vendor Google
Mainboard -> Mainboard vendor Veyron_Speedy (ASUS C201 Chromebook)
Mainboard -> ROM chip size 4096 KB (4 MB)
Payload -> Add a payload Depthcharge

Build

Now that you have a .config file you are ready to build coreboot.

make arm --jobs=12

Sidenotes

You may be able to cross compile coreboot. This means, build the rom file on a none-arm machine. You will need to install the crossgcc tools, using the command below.

make crossgcc-arm CPUS=4

Sources:

  1. https://www.coreboot.org/Git
  2. https://mail.coreboot.org/pipermail/coreboot/2018-February/086242.html
  3. https://www.coreboot.org/Payloads
  4. https://code.georgi.software/coreboot/coreboot/commit/9125073d2af2e1c34977c9caeb5f9c5710d5b9c4?view=parallel
  5. https://www.coreboot.org/Build_HOWTO
  6. https://www.coreboot.org/Coreboot_Options
# This is the config file that came with an ASUS Chromebook C201. It may not be
# exactly the same for every model, but they should be similar.
# This image was built using git revision b13b1ce8e9eda581f33d9094c11b89d2f87538bf
CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="google/veyron_speedy"
CONFIG_MAINBOARD_PART_NUMBER="Veyron_Speedy"
CONFIG_MAINBOARD_VENDOR="Google"
CONFIG_MAX_CPUS=1
CONFIG_RAMTOP=0x200000
CONFIG_HEAP_SIZE=0x4000
CONFIG_RAMBASE=0x100000
CONFIG_STACK_SIZE=0x0
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_UDELAY_IO=y
CONFIG_SERIAL_CPU_INIT=y
CONFIG_ACPI_SSDTX_NUM=0
CONFIG_VENDOR_SPECIFIC_OPTIONS=y
CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY=y
CONFIG_VBOOT_RAMSTAGE_INDEX=0x3
CONFIG_BOOT_MEDIA_SPI_BUS=2
CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x0
CONFIG_FLASHMAP_OFFSET=0x100000
CONFIG_DRIVER_TPM_I2C_BUS=0x1
CONFIG_DRIVER_TPM_I2C_ADDR=0x20
CONFIG_VBOOT_ROMSTAGE_INDEX=2
CONFIG_PMIC_BUS=0
CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US=100
CONFIG_LOGICAL_CPUS=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
CONFIG_CPU_ADDR_BITS=36
CONFIG_BOARD_ROMSIZE_KB_4096=y
CONFIG_COREBOOT_ROMSIZE_KB_4096=y
CONFIG_COREBOOT_ROMSIZE_KB=4096
CONFIG_ROM_SIZE=0x400000
CONFIG_ARCH_ARM=y
CONFIG_X86_BOOTBLOCK_SIMPLE=y
CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
CONFIG_HPET_ADDRESS=0xfed00000
CONFIG_ID_SECTION_OFFSET=0x80
CONFIG_ARCH_BOOTBLOCK_ARM=y
CONFIG_ARCH_VERSTAGE_ARM=y
CONFIG_ARCH_ROMSTAGE_ARM=y
CONFIG_ARCH_RAMSTAGE_ARM=y
CONFIG_ARCH_BOOTBLOCK_ARM_V7=y
CONFIG_ARCH_VERSTAGE_ARM_V7=y
CONFIG_ARCH_ROMSTAGE_ARM_V7=y
CONFIG_ARCH_RAMSTAGE_ARM_V7=y
CONFIG_XIP_ROM_SIZE=0x10000
CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
CONFIG_BOOTBLOCK_CPU_INIT="soc/rockchip/rk3288/bootblock.c"
CONFIG_SMM_TSEG_SIZE=0
CONFIG_CACHE_ROM=y
CONFIG_VIDEO_MB=0
CONFIG_CBFS_SIZE=0x100000
CONFIG_SPI_FLASH=y
CONFIG_SERIRQ_CONTINUOUS_MODE=y
CONFIG_EC_GOOGLE_CHROMEEC=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP=0
CONFIG_SOC_ROCKCHIP_RK3288=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMMON_CBFS_SPI_WRAPPER=y
CONFIG_COMPILER_GCC=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_DYNAMIC_CBMEM=y
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION=y
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
CONFIG_PCI_BUS_SEGN_BITS=0
CONFIG_FRAMEBUFFER_VESA_MODE_117=y
CONFIG_FRAMEBUFFER_VESA_MODE=0x117
CONFIG_ELOG=y
CONFIG_ELOG_FLASH_BASE=0x0
CONFIG_ELOG_AREA_SIZE=0x1000
CONFIG_ELOG_FULL_THRESHOLD=0xC00
CONFIG_ELOG_SHRINK_SIZE=0x400
CONFIG_I2C_TPM=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_TPM=y
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_EARLY_CONSOLE=y
CONFIG_CONSOLE_CBMEM=y
CONFIG_CONSOLE_FIXED_PRERAM_CBMEM_BUFFER=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
CONFIG_HAVE_UART_MEMORY_MAPPED=y
CONFIG_HAVE_UART_SPECIAL=y
CONFIG_HAVE_HARD_RESET=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_GENERIC_UDELAY=y
CONFIG_CACHE_ROM_SIZE=0x100000
CONFIG_MAX_PIRQ_LINKS=4
CONFIG_PAYLOAD_NONE=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_BOARD_ID_SUPPORT=y
CONFIG_RAM_CODE_SUPPORT=y
CONFIG_CHROMEOS=y
CONFIG_CHROMEOS_VBNV_EC=y
CONFIG_CHROMEOS_RAMOOPS=y
CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_VBOOT_BOOT_LOADER_INDEX=0x0
CONFIG_VBOOT2_VERIFY_FIRMWARE=y
CONFIG_RETURN_FROM_VERSTAGE=y
CONFIG_MAX_REBOOT_CNT=3
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