Should this work?

question.py

from nmigen import *
from nmigen.back import verilog

s = Signal(128)
i = Signal(range(128))
d = Signal(16)
m = Module()
m.d.sync += s.bit_select(i, len(s)).word_select(1, 16).eq(d)
# No exception from either of the following:
# m.d.sync += s.bit_select(i, len(s)).eq(d)
# m.d.sync += s.word_select(1, 16).eq(d)
verilog.convert(m.elaborate(None))

"""
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "/home/awygle/nmigen/nmigen/back/verilog.py", line 56, in convert
    rtlil_text = rtlil.convert(*args, **kwargs)
  File "/home/awygle/nmigen/nmigen/back/rtlil.py", line 1059, in convert
    il_text, name_map = convert_fragment(fragment, name)
  File "/home/awygle/nmigen/nmigen/back/rtlil.py", line 1053, in convert_fragment
    _convert_fragment(builder, fragment, name_map, hierarchy=(name,))
  File "/home/awygle/nmigen/nmigen/back/rtlil.py", line 946, in _convert_fragment
    stmt_compiler(group_stmts)
  File "/home/awygle/nmigen/nmigen/hdl/xfrm.py", line 232, in __call__
    return self.on_statement(stmt)
  File "/home/awygle/nmigen/nmigen/back/rtlil.py", line 787, in on_statement
    super().on_statement(stmt)
  File "/home/awygle/nmigen/nmigen/hdl/xfrm.py", line 220, in on_statement
    new_stmt = self.on_statements(stmt)
  File "/home/awygle/nmigen/nmigen/back/rtlil.py", line 805, in on_statements
    self.on_statement(stmt)
  File "/home/awygle/nmigen/nmigen/back/rtlil.py", line 787, in on_statement
    super().on_statement(stmt)
  File "/home/awygle/nmigen/nmigen/hdl/xfrm.py", line 209, in on_statement
    new_stmt = self.on_Assign(stmt)
  File "/home/awygle/nmigen/nmigen/back/rtlil.py", line 735, in on_Assign
    self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec)
  File "/home/awygle/nmigen/nmigen/hdl/xfrm.py", line 127, in __call__
    return self.on_value(value)
  File "/home/awygle/nmigen/nmigen/hdl/xfrm.py", line 104, in on_value
    new_value = self.on_Slice(value)
  File "/home/awygle/nmigen/nmigen/back/rtlil.py", line 402, in on_Slice
    sigspec = self._prepare_value_for_Slice(value.value)
  File "/home/awygle/nmigen/nmigen/back/rtlil.py", line 665, in _prepare_value_for_Slice
    assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat))
AssertionError
"""