awygle

def freq_check(module, ports, freq):
    from nmigen._toolchain.yosys import find_yosys
    from nmigen._toolchain import require_tool
    from nmigen.back import verilog
    from tempfile import mkstemp
    import os
    from subprocess import Popen, PIPE

    clean_ports = []
    print(ports)

awygle

import sys

from nmigen import *;
from nmigen.build import *
from nmigen.vendor.lattice_ecp5 import *
from nmigen_boards.resources import *
from nmigen.back import *
from nmigen_boards.versa_ecp5 import *
from nmigen.lib.cdc import FFSynchronizer

awygle

arch n64.cpu
endian msb
fill 1052672 // Set ROM Size

// Setup Frame Buffer
constant SCREEN_X(320)
constant SCREEN_Y(240)
constant BYTES_PER_PIXEL(2)

// Setup Characters

awygle

#version 450

layout(local_size_x = 1024) in;

layout(set = 0, binding = 0) buffer Buffer0 {
uint[16] state_in;
};

layout(set = 0, binding = 1) buffer Buffer1 {
uint x_offset;

awygle

{
  "creator": "Yosys 0.9+1706 (git sha1 4ef8c4b3, clang 6.0.0-1ubuntu2 -fPIC -Os)",
  "modules": {
    "ALU54B": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "cells_not_processed": "00000000000000000000000000000001",
        "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:44"
      },
      "ports": {

awygle

+ [ -n  ]
+ : yosys
+ : nextpnr-ecp5
+ : ecppack
+ yosys -l top.rpt top.ys
+ nextpnr-ecp5 --log top.tim --12k --package CABGA256 --speed 6 --json top.json --lpf top.lpf --textcfg top.config


Info: Logic utilisation before packing:
Info:     Total LUT4s:     10455/24288    43%

awygle

import sys

from nmigen import *;
from nmigen.build import *
from nmigen.vendor.lattice_ecp5 import *
from nmigen_boards.resources import *
from nmigen.back import *;
from nmigen_boards.versa_ecp5 import *;

from udptherbone.stream import *

awygle

    def elaborate(self, platform):
        m = Module()

        # Data clock edge detection
        dclk_last = Signal()

        m.d.sync += dclk_last.eq(self.dclk)

        dclk_redge = Signal()
        m.d.comb += dclk_redge.eq(self.dclk & ~dclk_last)

awygle

from nmigen import *
import nmigen.back
from nmigen.cli import main

class MVCE(Elaboratable):
    def __init__(self):
        self.write_en = Signal()

    def elaborate(self, platform):
        m = Module()

awygle

My concept is to create a generic graph traversal / dataflow infrastructure, and then define 3-4 concrete types depending on where we are in the flow.

At the core of this we have a general graph struct:

struct Graph<T> {
  root: GraphNode<T>,
  ...
}

And a GraphNode trait: