invalid_fsm.py

    def elaborate(self, platform):
        m = Module()

        # Data clock edge detection
        dclk_last = Signal()

        m.d.sync += dclk_last.eq(self.dclk)

        dclk_redge = Signal()
        m.d.comb += dclk_redge.eq(self.dclk & ~dclk_last)
        dclk_fedge = Signal()
        m.d.comb += dclk_fedge.eq(~self.dclk & dclk_last)

        m.d.sync += self.data_o.eq(self.input)

        # default consumed to false
        m.d.sync += self.consumed.eq(0)

        with m.If(self.write_en):
            # TX state machine
            with m.FSM() as fsm:
                """
                INIT STATE:
                data_e remains low until falling edge
                """
                with m.State("Init"):
                    with m.If(dclk_fedge):
                        # drive out, advance state
                        m.d.sync += self.data_e.eq(1)
                        m.next = "Active" # ???
                """
                ACTIVE STATE:
                data_e is high, pulse consumed on rising edge
                """
                with m.State("Active"):
                    with m.If(dclk_redge):
                        # just pulse the consumed bit
                        m.d.sync += self.consumed.eq(1)
        with m.Else():
            # RX state machine - reset TX state machine
            m.next = "Init"
            """
            data_e is low
            update output on rising edge
            """
            m.d.sync += self.data_e.eq(0)
            with m.If(dclk_redge):
                m.d.sync += self.output.eq(self.data_i)

        return m