practicalswift

#!/usr/bin/env python3

# $ ./nakamotos-wild-mouse.py
# Match between the reverse engineered vaccine and the Biontech Pfizer vaccine when using codon optimization for species:
# * Homo sapiens: 91.07%
# * Mus musculus molossinus (Japanese wild mouse): 91.42% (laboratory mice are usually of the species mus musculus)
#
# The Times 01/Jan/2021 Nakamoto's wild mouse on brink of saving humanity

import dnachisel

vojtamolda

Differentiable Shallow Water PDE Solver

This repository contains source code of a shallow water partial differential equation (PDE) solver. The solver is written in differentiable Swift which allows end-to-end propagation of derivatives through time. In physics this kind of solution is traditionally called adjoint and it unlocks a new class of algorithms for optimal control of PDEs.

More details about the PDE and how to derive it from general Navier-Stokes equations can found for example on Wikipedia.

The following notebook demonstrates how the differentiability of the solver can be leveraged to solve an otherwise tricky optimal control problem.

Showcase.ipynb [![ColabBadge]][ShowcaseColabLink]

rxwei

See the official Differentiable Programming Manifesto instead.

marcan

Testing done using a Canon EOS 600D and a Canon EF-S18-55mm f/3.5-5.6 IS II.

Pinout

1. VBAT
2. DET (common with P-GND on lens side)
3. P-GND
4. VDD
5. DCL
6. DLC

nadavrot

High-Performance Matrix Multiplication

This is a short post that explains how to write a high-performance matrix multiplication program on modern processors. In this tutorial I will use a single core of the Skylake-client CPU with AVX2, but the principles in this post also apply to other processors with different instruction sets (such as AVX512).

Intro

Matrix multiplication is a mathematical operation that defines the product of

Catfish-Man

#import <Foundation/Foundation.h>
#import <assert.h>

//Compile with `clang -Os -framework Foundation -fno-objc-arc inlinestorage.m -o inline, run with `inline clever` or `inline naive`

/*
 NaiveArray implements a simple immutable NSArray-like interface in probably the most obvious way: store a pointer to a C array of objects
 */
@interface NaiveArray : NSObject {
    NSUInteger count;

lattner

Swift Concurrency Manifesto

Author: Chris Lattner

Chinese Translation by Jason Yu

Contents

• Introduction
• Overall Vision

jhaberstro

http://courses.cms.caltech.edu/cs179/
http://www.amd.com/Documents/GCN_Architecture_whitepaper.pdf
https://community.arm.com/graphics/b/blog
http://cdn.imgtec.com/sdk-documentation/PowerVR+Hardware.Architecture+Overview+for+Developers.pdf
http://cdn.imgtec.com/sdk-documentation/PowerVR+Series5.Architecture+Guide+for+Developers.pdf
https://www.imgtec.com/blog/a-look-at-the-powervr-graphics-architecture-tile-based-rendering/
https://www.imgtec.com/blog/the-dr-in-tbdr-deferred-rendering-in-rogue/
http://developer.amd.com/tools-and-sdks/opencl-zone/amd-accelerated-parallel-processing-app-sdk/opencl-optimization-guide/#50401334_pgfId-412605
https://fgiesen.wordpress.com/2011/07/09/a-trip-through-the-graphics-pipeline-2011-index/
https://community.arm.com/graphics/b/documents/posts/moving-mobile-graphics#siggraph2015

Gankra

Swift Ownership Manifesto TL;DR

Most of the manifesto is background and detailed definitions -- if you're confused or want details, read the manifesto!

https://lists.swift.org/pipermail/swift-evolution/Week-of-Mon-20170213/032155.html

Note also that manifestos aren't complete proposals -- syntax and details may change!

One piece of background: inout is kinda complicated because it can be used on computed properties -- foo(&val.x) might be sugar for

pervognsen

One thing that surprises newer programmers is that the older 8-bit microcomputers from the 70s and 80s were designed to run at the speed of random memory access to DRAM and ROM. The C64 was released in 1982 when I was born and its 6502 CPU ran at 1 MHz (give or take depending on NTSC vs PAL). It had a 2-stage pipelined design that was designed to overlap execution and instruction fetch for the current and next instruction. Cycle counting was simple to understand and master since it was based almost entirely on the number of memory accesses (1 cycle each), with a 1-cycle penalty for taken branches because of the pipelined instruction fetch for the next sequential instruction. So, the entire architecture was based on keeping the memory subsystem busy 100% of the time by issuing a read or write every cycle. One-byte instructions with no memory operands like INX still take the minimum 2 cycles per instruction and end up redundantly issuing the same memory request two cycles in a row.