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brabect1 / tcl_reuse_components.rst
Last active July 15, 2023 13:07
Tcl Modules and Packages #tcl
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brabect1 / sta_cdc_paths.rst
Last active May 4, 2024 10:52
Timing constraints for clock-domain crossings. #sta #cdc
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brabect1 / gpg.rst
Last active August 14, 2022 12:57
gpg usage for file encrypting and decrypting #gpg

Using GPG

# encrypt file
# (-armor will create an ASCII file)
gpg --encrypt --sign --armor -r <e-mail> <file>

# encrypt multiple files
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brabect1 / coding_rtl_for_phys_impl.rst
Last active July 6, 2023 07:17
Tips for physical implementation friendly RTL design. #sta #rtl

RTL Coding Tips for Easier Physical Implementation

Quite a few digital design engineers limit their activities to architecture design and RTL coding. Missing first hand experience with later design phases is then easily detected by how much their code and architecture complicates physical implementation. Areas where this surfaces most often are clock/reset schemes, clock domain crossings (CDC) and scan/DFT aspects.

Gate Instantiations

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brabect1 / liberty_cell_modes.rst
Last active September 28, 2021 08:30
Aspects of modeling cell operation modes in Liberty. #sta #liberty

Cell Operation Modes in Liberty

Modeling complex hard IPs (for use in digital physical implementation and verification) can often exercise semantic limits of the modeling mechanisms. Cell operating mode in timing libraries (i.e. Liberty) is one of those lesser known aspects that may help with IP timing modeling.

Mode Definition

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brabect1 / sta_data_checks.rst
Last active May 4, 2024 11:09
STA of data-to-data constraints (or non-sequential timing arcs). #sta #non_seq

STA Data-to-Data Checks

STA's primary function is to check a data signal timing to a clock signal timing, such as setup and hold constraints that require the data signal to remain stable around the active clock edge. In certain cases, we need to constrain the data change not to a clock event but another data signal event. These are called data-to-data checks. You can find them frequently in hard macros with asynchronous interfaces; but also in flip-flops with both asynchronous set and reset to enforce priority of one over the other.

Data-to-data checks can be expressed as user constraints (set_data_check) or as Liberty timing arcs

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brabect1 / sta_duty_jitter.rst
Last active November 1, 2020 20:47
Discussing optins for constraining duty cycle jitter. #sta #jitter #duty

Constraining Duty Cycle Jitter

As a duty cycle jitter we understand a half-cycle variance in timing.

Say we have 1:1 duty cycle with 20ns period and a 2ns (or 10%) duty cycle jitter. If the clock rises at 0ns, the fall will come somewhere between 8ns and 12ns. Or, you may say the clock duty cycle varies from 40% to 60%.

Now the question is how you model that in STA?

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brabect1 / sta_pll_example.rst
Last active March 27, 2024 21:23
Discuss constraining PLL generated clocks in modern STA tools. #sta #pll

STA PLL Timing

Phase-Locked Loop (PLL) is used to compensate delay in its feedback path, which can be used for different purposes. The most frequent uses are to compensate the clock tree delay/depth or to compensate the IO delay (or both).

A decade ago, accounting for the compensation in STA timing used to be a haedache. See P. Zimmer. Working with PLLs in PrimeTime – avoiding the phase locked oops, SNUG San Jose 2005, http://www.zimmerdesignservices.com/mydownloads/zimmer_pll_update_051405.pdf

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brabect1 / panflute_latex_filters.rst
Last active June 27, 2020 14:55
Creating pandoc filters with panflute for LaTeX #pandoc #panflute #latex

Pandoc LaTeX Filters with panflute

Panflute is a Python module for creating pandoc filters.

LaTeX Filters

A basic panflute filter, that actually does nothing, looks like follows:

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brabect1 / verilog_dependencies.rst
Last active May 4, 2024 11:10
Discovering Verilog files dependencies #verilog #systemverilog #verilog-perl

Discovering (System)Verilog Dependencies

The Verilog-perl module comes with some utilities to help you orient yourself in an alien code.

One of the first things you normally do is to understend the module dependencies. That is, what module instantiates other modules. You can do this easily as follows:

vhier -sv --no-missing --missing-modules  --forest <files>