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diff --git a/lib/Target/AVR/AVRRegisterInfo.h b/lib/Target/AVR/AVRRegisterInfo.h
index f8fefb85968..611d739ee83 100644
--- a/lib/Target/AVR/AVRRegisterInfo.h
+++ b/lib/Target/AVR/AVRRegisterInfo.h
@@ -51,6 +51,11 @@ public:
   /// Splits a 16-bit `DREGS` register into the lo/hi register pair.
   /// \param Reg A 16-bit register to split.
   void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
+
+  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {

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diff --git a/lib/Target/AVR/AVRInstrInfo.td b/lib/Target/AVR/AVRInstrInfo.td
index a2129cc0e2e..601cfa8d861 100644
--- a/lib/Target/AVR/AVRInstrInfo.td
+++ b/lib/Target/AVR/AVRInstrInfo.td
@@ -1222,7 +1222,7 @@ isReMaterializable = 1 in
   // ldd Rd,   P+q
   // ldd Rd+1, P+q+1
   let Constraints = "@earlyclobber $dst" in
-  def LDDWRdPtrQ : Pseudo<(outs DREGS:$dst),
+  def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_Z:$dst),

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	.text
	.file	"rust-avr-bug-92.1.ll"
	.globl	retstruct1              ; -- Begin function retstruct1
	.p2align	1
	.type	retstruct1,@function
retstruct1:                             ; @retstruct1
; %bb.0:                                ; %start
	ldi	r22, 0
	ldi	r23, 0
	ldi	r24, 0

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; RUN: llc < %s -march=avr | FileCheck %s

; CHECK-LABEL: retstruct1
define { i8, i32 } @retstruct1() {
start:
  ret { i8, i32 } zeroinitializer
}

; CHECK-LABEL: retstruct2
define { i16, i32 } @retstruct2() {

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diff --git a/lib/Target/AVR/AVRISelLowering.cpp b/lib/Target/AVR/AVRISelLowering.cpp
index e0bb2f317d1..4dc7efaa51c 100644
--- a/lib/Target/AVR/AVRISelLowering.cpp
+++ b/lib/Target/AVR/AVRISelLowering.cpp
@@ -1374,7 +1374,24 @@ AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
   // Reverse splitted return values to get the "big endian" format required
   // to agree with the calling convention ABI.
   if (e > 1) {
-    std::reverse(RVLocs.begin(), RVLocs.end());
+    // some hackery because SelectionDAGBuilder does not split up arguments properly

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Index: lib/Target/AVR/AVRISelLowering.cpp
===================================================================
--- lib/Target/AVR/AVRISelLowering.cpp  (revision 326572)
+++ lib/Target/AVR/AVRISelLowering.cpp  (working copy)
@@ -345,6 +345,8 @@
   case MVT::i64:
     LC = IsSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64;
     break;
+  case MVT::i128:
+    LC = IsSigned ? RTLIB::SDIVREM_I128 : RTLIB::UDIVREM_I128;

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diff --git a/lib/Target/AVR/AVRISelLowering.cpp b/lib/Target/AVR/AVRISelLowering.cpp
index 7ac8a136e6b..e0bb2f317d1 100644
--- a/lib/Target/AVR/AVRISelLowering.cpp
+++ b/lib/Target/AVR/AVRISelLowering.cpp
@@ -1346,7 +1346,7 @@ AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
   CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
 
   auto CCFunction = CCAssignFnForReturn(CallConv);
-  return CCInfo.CheckReturn(Outs, CCFunction);
+  return !MF.getFunction().getReturnType()->isStructTy() && CCInfo.CheckReturn(Outs, CCFunction);

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diff --git a/lib/Target/AVR/AVRISelLowering.cpp b/lib/Target/AVR/AVRISelLowering.cpp
index 7ac8a136e6b..4f7d3d6a815 100644
--- a/lib/Target/AVR/AVRISelLowering.cpp
+++ b/lib/Target/AVR/AVRISelLowering.cpp
@@ -1371,16 +1371,12 @@ AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
   MachineFunction &MF = DAG.getMachineFunction();
   unsigned e = RVLocs.size();
 
-  // Reverse splitted return values to get the "big endian" format required
-  // to agree with the calling convention ABI.

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; RUN: llc < %s -march=avr | FileCheck %s

declare i8 @do_something(i8 %val)

define { i1, i8 } @main(i8) #2 {
; CHECK-LABEL: main
entry:
  %1 = call zeroext i8 @do_something(i8 zeroext %0)
  %2 = insertvalue { i1, i8 } { i1 true, i8 undef }, i8 %1, 1
  ret { i1, i8 } %2

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Index: lib/Target/AVR/AVRISelLowering.cpp
===================================================================
--- lib/Target/AVR/AVRISelLowering.cpp  (revision 325378)
+++ lib/Target/AVR/AVRISelLowering.cpp  (working copy)
@@ -867,10 +867,11 @@
 
 /// For each argument in a function store the number of pieces it is composed
 /// of.
-static void parseFunctionArgs(const Function *F, const DataLayout *TD,
+static void parseFunctionArgs(const SmallVectorImpl<ISD::InputArg> &Ins,