gistfile1.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:01:31 01/20/2015 
// Design Name: 
// Module Name:    mcp3202 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mcp3202(
    input clk,
    input data,
    output reg spiclk,
    output reg cs,
    output reg [3:0] leds,
    output reg tx,
	 input button,
	 input button2
    );

reg [15:0] spicount;
reg [15:0] cscount;
reg [11:0] adcdata;
reg [15:0] uartcount;
reg [15:0] uartstate;
reg uartclk;
reg rd_clk;
reg wr_clk;
reg wr_en;
reg rd_en;
reg unloading;
reg loading;
reg rst;
wire full;
wire empty;
wire [7:0] doubt;

fifo adcfifo (
  .rst(rst), // input rst
  .rd_clk(uartclk), // input wr_clk
  .wr_clk(spiclk),
  .din(adcdata[11:4]), // input [7 : 0] din
  .wr_en(wr_clk), // input wr_en
  .rd_en(rd_clk), // input rd_en
  .dout(doubt), // output [7 : 0] dout
  .full(full), // output full
  .empty(empty) // output empty
);

initial begin
	spicount <= 16'd0;
	cscount <= 16'd0;
	adcdata <= 12'd0;
	spiclk <= 1'b1;
	cs <= 1'b1;
	leds <= 4'b0000; 
	tx <= 1'b1;
	unloading <= 1'b0;
	rd_clk <= 1'b0;
	wr_clk <= 1'b0;
	uartclk <= 1'b0;
	uartcount <= 16'd0;
	uartstate <= 16'd0;
	loading <= 1'b0;
	rst <= 1'b1;
	rd_en <= 1'b1;
	wr_en <= 1'b1;
end

always @(posedge clk) begin
	leds[0] <= full;
	leds[1] <= empty;
	leds[3:2] <= doubt[1:0];
	rst <= 1'b0;
	spicount <= spicount + 1'b1;
	uartcount <= uartcount + 1'b1;
	if (spicount == 16'd16) spiclk <= 1'b0;
	else if (spicount == 16'd33) begin
		spiclk <= 1'b1;
		spicount <= 16'd0;
	end
	if (uartcount == 16'd117) uartclk <= 1'b1;
	else if (uartcount == 16'd234) begin
		uartclk <= 1'b0;
		uartcount <= 16'd0;
	end
end

always @(posedge uartclk) begin
	if (full & button) unloading <= 1'b1;
	if (unloading) begin
		uartstate <= uartstate + 1'b1;
		if (uartstate == 16'd0) begin 
			if (~empty) begin
				rd_clk <= 1'b1;
				tx <= 1'b0;
			end else unloading <= 1'b0;
		end else if (uartstate == 16'd1) begin
			rd_clk <= 1'b0;
			tx <= doubt[0];
		end else if (uartstate == 16'd2) tx <= doubt[1];
		else if (uartstate <= 16'd3) tx <= doubt[2];
		else if (uartstate <= 16'd4) tx <= doubt[3];
		else if (uartstate <= 16'd5) tx <= doubt[4];
		else if (uartstate <= 16'd6) tx <= doubt[5];
		else if (uartstate <= 16'd7) tx <= doubt[6];
		else if (uartstate <= 16'd8) tx <= doubt[7];
		else if (uartstate <= 16'd9) begin
			tx <= 1'b1;
		end else if (uartstate <= 16'd10) uartstate <= 16'd0;
	end
end

always @(posedge spiclk) begin
	cscount <= cscount + 1'b1;
	if (button2 && empty) loading <= 1'b1;
	if (full) loading <= 1'b0;
	if (cscount == 16'd0) begin 
		cs <= 1'b0;
		if (wr_clk == 1'b1) begin 
			wr_clk <= 1'b0;
		end
	end
	else if (cscount == 16'd4) adcdata[11] <= data;
	else if (cscount == 16'd5) adcdata[10] <= data;
	else if (cscount == 16'd6) adcdata[9] <= data;
	else if (cscount == 16'd7) adcdata[8] <= data;
	else if (cscount == 16'd8) adcdata[7] <= data;
	else if (cscount == 16'd9) adcdata[6] <= data;
	else if (cscount == 16'd10) adcdata[5] <= data;
	else if (cscount == 16'd11) adcdata[4] <= data;
	else if (cscount == 16'd12) adcdata[3] <= data;
	else if (cscount == 16'd13) adcdata[2] <= data;
	else if (cscount == 16'd14) adcdata[1] <= data;
	if (cscount == 16'd15) begin
		adcdata[0] <= data;
		if (~unloading && ~full && loading) begin
			wr_clk <= 1'b1;
		end
		cs <= 1'b1;
		cscount <= 16'd0;
	end
end

endmodule