Created
October 12, 2017 09:25
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module Rx_top(clk, serial_in, received_data, rx_error, data_is_available, data_is_valid); // serial input, parallel output | |
input clk, serial_in; | |
output reg rx_error, data_is_available, data_is_valid; | |
output reg [7:0] received_data; | |
// determines when to sample data | |
RxUART rx (.clk(clk), .serial_in(serial_in), .data_is_available(data_is_available), .data_is_valid(data_is_valid), .rx_error(rx_error)); | |
// handles data sampling | |
shift_register SIPO (.clk(clk), .serial_in(serial_in), .data_is_available(data_is_available), .received_data(received_data)); | |
// even parity check | |
check_parity cp (.clk(clk), .serial_in(serial_in), .data_is_valid(data_is_valid), .rx_error(rx_error)); | |
endmodule |
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