ILA waveforms for https://github.com/promach/riffa/tree/development Remember to Edit->Toggle Trace Hier

riffa_full_duplex.gtkw

[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Mon Aug  6 12:39:05 2018
[*]
[dumpfile] "/home/phung/Documents/fpga_overlay/riffa/fpga/altera/de4/DE4Gen2x8If128/prj/riffa_full_duplex_not_working.vcd"
[dumpfile_mtime] "Fri Aug  3 10:48:16 2018"
[dumpfile_size] 753880
[savefile] "/home/phung/Documents/fpga_overlay/riffa/fpga/altera/de4/DE4Gen2x8If128/prj/riffa_full_duplex_not_working.gtkw"
[timestart] 0
[size] 1920 1115
[pos] 0 0
*-22.908167 5095000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] riffa.
[treeopen] riffa.engine_layer_inst.
[treeopen] riffa.engine_layer_inst.rx_engine_classic_inst.
[treeopen] riffa.engine_layer_inst.tx_engine_classic_inst.
[treeopen] riffa.engine_layer_inst.tx_engine_classic_inst.txr_engine_inst.
[treeopen] riffa.engine_layer_inst.tx_engine_classic_inst.txr_engine_inst.txr_formatter_inst.
[treeopen] riffa.riffa_inst.
[treeopen] riffa.riffa_inst.channels[0].
[treeopen] riffa.riffa_inst.channels[0].channel.
[treeopen] riffa.riffa_inst.channels[0].channel.channel.
[treeopen] riffa.riffa_inst.channels[0].channel.channel.rxPort.
[treeopen] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.
[treeopen] riffa.riffa_inst.intr.
[treeopen] riffa.riffa_inst.reg_inst.
[treeopen] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.
[treeopen] test_channels[0].
[sst_width] 50
[signals_width] 774
[sst_expanded] 0
[sst_vpaned_height] 523
@28
test_channels[0].chnl_tester_i.CHNL_RX
test_channels[0].chnl_tester_i.CHNL_RX_ACK
test_channels[0].chnl_tester_i.CHNL_RX_CLK
@22
#{test_channels[0].chnl_tester_i.CHNL_RX_DATA[127:0]} test_channels[0].chnl_tester_i.CHNL_RX_DATA[127] test_channels[0].chnl_tester_i.CHNL_RX_DATA[126] test_channels[0].chnl_tester_i.CHNL_RX_DATA[125] test_channels[0].chnl_tester_i.CHNL_RX_DATA[124] test_channels[0].chnl_tester_i.CHNL_RX_DATA[123] test_channels[0].chnl_tester_i.CHNL_RX_DATA[122] test_channels[0].chnl_tester_i.CHNL_RX_DATA[121] test_channels[0].chnl_tester_i.CHNL_RX_DATA[120] test_channels[0].chnl_tester_i.CHNL_RX_DATA[119] test_channels[0].chnl_tester_i.CHNL_RX_DATA[118] test_channels[0].chnl_tester_i.CHNL_RX_DATA[117] test_channels[0].chnl_tester_i.CHNL_RX_DATA[116] test_channels[0].chnl_tester_i.CHNL_RX_DATA[115] test_channels[0].chnl_tester_i.CHNL_RX_DATA[114] test_channels[0].chnl_tester_i.CHNL_RX_DATA[113] test_channels[0].chnl_tester_i.CHNL_RX_DATA[112] test_channels[0].chnl_tester_i.CHNL_RX_DATA[111] test_channels[0].chnl_tester_i.CHNL_RX_DATA[110] test_channels[0].chnl_tester_i.CHNL_RX_DATA[109] test_channels[0].chnl_tester_i.CHNL_RX_DATA[108] test_channels[0].chnl_tester_i.CHNL_RX_DATA[107] test_channels[0].chnl_tester_i.CHNL_RX_DATA[106] test_channels[0].chnl_tester_i.CHNL_RX_DATA[105] test_channels[0].chnl_tester_i.CHNL_RX_DATA[104] test_channels[0].chnl_tester_i.CHNL_RX_DATA[103] test_channels[0].chnl_tester_i.CHNL_RX_DATA[102] test_channels[0].chnl_tester_i.CHNL_RX_DATA[101] test_channels[0].chnl_tester_i.CHNL_RX_DATA[100] test_channels[0].chnl_tester_i.CHNL_RX_DATA[99] test_channels[0].chnl_tester_i.CHNL_RX_DATA[98] test_channels[0].chnl_tester_i.CHNL_RX_DATA[97] test_channels[0].chnl_tester_i.CHNL_RX_DATA[96] test_channels[0].chnl_tester_i.CHNL_RX_DATA[95] test_channels[0].chnl_tester_i.CHNL_RX_DATA[94] test_channels[0].chnl_tester_i.CHNL_RX_DATA[93] test_channels[0].chnl_tester_i.CHNL_RX_DATA[92] test_channels[0].chnl_tester_i.CHNL_RX_DATA[91] test_channels[0].chnl_tester_i.CHNL_RX_DATA[90] test_channels[0].chnl_tester_i.CHNL_RX_DATA[89] test_channels[0].chnl_tester_i.CHNL_RX_DATA[88] test_channels[0].chnl_tester_i.CHNL_RX_DATA[87] test_channels[0].chnl_tester_i.CHNL_RX_DATA[86] test_channels[0].chnl_tester_i.CHNL_RX_DATA[85] test_channels[0].chnl_tester_i.CHNL_RX_DATA[84] test_channels[0].chnl_tester_i.CHNL_RX_DATA[83] test_channels[0].chnl_tester_i.CHNL_RX_DATA[82] test_channels[0].chnl_tester_i.CHNL_RX_DATA[81] test_channels[0].chnl_tester_i.CHNL_RX_DATA[80] test_channels[0].chnl_tester_i.CHNL_RX_DATA[79] test_channels[0].chnl_tester_i.CHNL_RX_DATA[78] test_channels[0].chnl_tester_i.CHNL_RX_DATA[77] test_channels[0].chnl_tester_i.CHNL_RX_DATA[76] test_channels[0].chnl_tester_i.CHNL_RX_DATA[75] test_channels[0].chnl_tester_i.CHNL_RX_DATA[74] test_channels[0].chnl_tester_i.CHNL_RX_DATA[73] test_channels[0].chnl_tester_i.CHNL_RX_DATA[72] test_channels[0].chnl_tester_i.CHNL_RX_DATA[71] test_channels[0].chnl_tester_i.CHNL_RX_DATA[70] test_channels[0].chnl_tester_i.CHNL_RX_DATA[69] test_channels[0].chnl_tester_i.CHNL_RX_DATA[68] test_channels[0].chnl_tester_i.CHNL_RX_DATA[67] test_channels[0].chnl_tester_i.CHNL_RX_DATA[66] test_channels[0].chnl_tester_i.CHNL_RX_DATA[65] test_channels[0].chnl_tester_i.CHNL_RX_DATA[64] test_channels[0].chnl_tester_i.CHNL_RX_DATA[63] test_channels[0].chnl_tester_i.CHNL_RX_DATA[62] test_channels[0].chnl_tester_i.CHNL_RX_DATA[61] test_channels[0].chnl_tester_i.CHNL_RX_DATA[60] test_channels[0].chnl_tester_i.CHNL_RX_DATA[59] test_channels[0].chnl_tester_i.CHNL_RX_DATA[58] test_channels[0].chnl_tester_i.CHNL_RX_DATA[57] test_channels[0].chnl_tester_i.CHNL_RX_DATA[56] test_channels[0].chnl_tester_i.CHNL_RX_DATA[55] test_channels[0].chnl_tester_i.CHNL_RX_DATA[54] test_channels[0].chnl_tester_i.CHNL_RX_DATA[53] test_channels[0].chnl_tester_i.CHNL_RX_DATA[52] test_channels[0].chnl_tester_i.CHNL_RX_DATA[51] test_channels[0].chnl_tester_i.CHNL_RX_DATA[50] test_channels[0].chnl_tester_i.CHNL_RX_DATA[49] test_channels[0].chnl_tester_i.CHNL_RX_DATA[48] test_channels[0].chnl_tester_i.CHNL_RX_DATA[47] test_channels[0].chnl_tester_i.CHNL_RX_DATA[46] test_channels[0].chnl_tester_i.CHNL_RX_DATA[45] test_channels[0].chnl_tester_i.CHNL_RX_DATA[44] test_channels[0].chnl_tester_i.CHNL_RX_DATA[43] test_channels[0].chnl_tester_i.CHNL_RX_DATA[42] test_channels[0].chnl_tester_i.CHNL_RX_DATA[41] test_channels[0].chnl_tester_i.CHNL_RX_DATA[40] test_channels[0].chnl_tester_i.CHNL_RX_DATA[39] test_channels[0].chnl_tester_i.CHNL_RX_DATA[38] test_channels[0].chnl_tester_i.CHNL_RX_DATA[37] test_channels[0].chnl_tester_i.CHNL_RX_DATA[36] test_channels[0].chnl_tester_i.CHNL_RX_DATA[35] test_channels[0].chnl_tester_i.CHNL_RX_DATA[34] test_channels[0].chnl_tester_i.CHNL_RX_DATA[33] test_channels[0].chnl_tester_i.CHNL_RX_DATA[32] test_channels[0].chnl_tester_i.CHNL_RX_DATA[31] test_channels[0].chnl_tester_i.CHNL_RX_DATA[30] test_channels[0].chnl_tester_i.CHNL_RX_DATA[29] test_channels[0].chnl_tester_i.CHNL_RX_DATA[28] test_channels[0].chnl_tester_i.CHNL_RX_DATA[27] test_channels[0].chnl_tester_i.CHNL_RX_DATA[26] test_channels[0].chnl_tester_i.CHNL_RX_DATA[25] test_channels[0].chnl_tester_i.CHNL_RX_DATA[24] test_channels[0].chnl_tester_i.CHNL_RX_DATA[23] test_channels[0].chnl_tester_i.CHNL_RX_DATA[22] test_channels[0].chnl_tester_i.CHNL_RX_DATA[21] test_channels[0].chnl_tester_i.CHNL_RX_DATA[20] test_channels[0].chnl_tester_i.CHNL_RX_DATA[19] test_channels[0].chnl_tester_i.CHNL_RX_DATA[18] test_channels[0].chnl_tester_i.CHNL_RX_DATA[17] test_channels[0].chnl_tester_i.CHNL_RX_DATA[16] test_channels[0].chnl_tester_i.CHNL_RX_DATA[15] test_channels[0].chnl_tester_i.CHNL_RX_DATA[14] test_channels[0].chnl_tester_i.CHNL_RX_DATA[13] test_channels[0].chnl_tester_i.CHNL_RX_DATA[12] test_channels[0].chnl_tester_i.CHNL_RX_DATA[11] test_channels[0].chnl_tester_i.CHNL_RX_DATA[10] test_channels[0].chnl_tester_i.CHNL_RX_DATA[9] test_channels[0].chnl_tester_i.CHNL_RX_DATA[8] test_channels[0].chnl_tester_i.CHNL_RX_DATA[7] test_channels[0].chnl_tester_i.CHNL_RX_DATA[6] test_channels[0].chnl_tester_i.CHNL_RX_DATA[5] test_channels[0].chnl_tester_i.CHNL_RX_DATA[4] test_channels[0].chnl_tester_i.CHNL_RX_DATA[3] test_channels[0].chnl_tester_i.CHNL_RX_DATA[2] test_channels[0].chnl_tester_i.CHNL_RX_DATA[1] test_channels[0].chnl_tester_i.CHNL_RX_DATA[0]
@28
test_channels[0].chnl_tester_i.CHNL_RX_DATA_REN
test_channels[0].chnl_tester_i.CHNL_RX_DATA_VALID
test_channels[0].chnl_tester_i.CHNL_RX_LAST
@24
#{test_channels[0].chnl_tester_i.CHNL_RX_OFF[30:0]} test_channels[0].chnl_tester_i.CHNL_RX_OFF[30] test_channels[0].chnl_tester_i.CHNL_RX_OFF[29] test_channels[0].chnl_tester_i.CHNL_RX_OFF[28] test_channels[0].chnl_tester_i.CHNL_RX_OFF[27] test_channels[0].chnl_tester_i.CHNL_RX_OFF[26] test_channels[0].chnl_tester_i.CHNL_RX_OFF[25] test_channels[0].chnl_tester_i.CHNL_RX_OFF[24] test_channels[0].chnl_tester_i.CHNL_RX_OFF[23] test_channels[0].chnl_tester_i.CHNL_RX_OFF[22] test_channels[0].chnl_tester_i.CHNL_RX_OFF[21] test_channels[0].chnl_tester_i.CHNL_RX_OFF[20] test_channels[0].chnl_tester_i.CHNL_RX_OFF[19] test_channels[0].chnl_tester_i.CHNL_RX_OFF[18] test_channels[0].chnl_tester_i.CHNL_RX_OFF[17] test_channels[0].chnl_tester_i.CHNL_RX_OFF[16] test_channels[0].chnl_tester_i.CHNL_RX_OFF[15] test_channels[0].chnl_tester_i.CHNL_RX_OFF[14] test_channels[0].chnl_tester_i.CHNL_RX_OFF[13] test_channels[0].chnl_tester_i.CHNL_RX_OFF[12] test_channels[0].chnl_tester_i.CHNL_RX_OFF[11] test_channels[0].chnl_tester_i.CHNL_RX_OFF[10] test_channels[0].chnl_tester_i.CHNL_RX_OFF[9] test_channels[0].chnl_tester_i.CHNL_RX_OFF[8] test_channels[0].chnl_tester_i.CHNL_RX_OFF[7] test_channels[0].chnl_tester_i.CHNL_RX_OFF[6] test_channels[0].chnl_tester_i.CHNL_RX_OFF[5] test_channels[0].chnl_tester_i.CHNL_RX_OFF[4] test_channels[0].chnl_tester_i.CHNL_RX_OFF[3] test_channels[0].chnl_tester_i.CHNL_RX_OFF[2] test_channels[0].chnl_tester_i.CHNL_RX_OFF[1] test_channels[0].chnl_tester_i.CHNL_RX_OFF[0]
@28
test_channels[0].chnl_tester_i.CHNL_TX
test_channels[0].chnl_tester_i.CHNL_TX_ACK
test_channels[0].chnl_tester_i.CHNL_TX_CLK
@22
#{test_channels[0].chnl_tester_i.CHNL_TX_DATA[127:0]} test_channels[0].chnl_tester_i.CHNL_TX_DATA[127] test_channels[0].chnl_tester_i.CHNL_TX_DATA[126] test_channels[0].chnl_tester_i.CHNL_TX_DATA[125] test_channels[0].chnl_tester_i.CHNL_TX_DATA[124] test_channels[0].chnl_tester_i.CHNL_TX_DATA[123] test_channels[0].chnl_tester_i.CHNL_TX_DATA[122] test_channels[0].chnl_tester_i.CHNL_TX_DATA[121] test_channels[0].chnl_tester_i.CHNL_TX_DATA[120] test_channels[0].chnl_tester_i.CHNL_TX_DATA[119] test_channels[0].chnl_tester_i.CHNL_TX_DATA[118] test_channels[0].chnl_tester_i.CHNL_TX_DATA[117] test_channels[0].chnl_tester_i.CHNL_TX_DATA[116] test_channels[0].chnl_tester_i.CHNL_TX_DATA[115] test_channels[0].chnl_tester_i.CHNL_TX_DATA[114] test_channels[0].chnl_tester_i.CHNL_TX_DATA[113] test_channels[0].chnl_tester_i.CHNL_TX_DATA[112] test_channels[0].chnl_tester_i.CHNL_TX_DATA[111] test_channels[0].chnl_tester_i.CHNL_TX_DATA[110] test_channels[0].chnl_tester_i.CHNL_TX_DATA[109] test_channels[0].chnl_tester_i.CHNL_TX_DATA[108] test_channels[0].chnl_tester_i.CHNL_TX_DATA[107] test_channels[0].chnl_tester_i.CHNL_TX_DATA[106] test_channels[0].chnl_tester_i.CHNL_TX_DATA[105] test_channels[0].chnl_tester_i.CHNL_TX_DATA[104] test_channels[0].chnl_tester_i.CHNL_TX_DATA[103] test_channels[0].chnl_tester_i.CHNL_TX_DATA[102] test_channels[0].chnl_tester_i.CHNL_TX_DATA[101] test_channels[0].chnl_tester_i.CHNL_TX_DATA[100] test_channels[0].chnl_tester_i.CHNL_TX_DATA[99] test_channels[0].chnl_tester_i.CHNL_TX_DATA[98] test_channels[0].chnl_tester_i.CHNL_TX_DATA[97] test_channels[0].chnl_tester_i.CHNL_TX_DATA[96] test_channels[0].chnl_tester_i.CHNL_TX_DATA[95] test_channels[0].chnl_tester_i.CHNL_TX_DATA[94] test_channels[0].chnl_tester_i.CHNL_TX_DATA[93] test_channels[0].chnl_tester_i.CHNL_TX_DATA[92] test_channels[0].chnl_tester_i.CHNL_TX_DATA[91] test_channels[0].chnl_tester_i.CHNL_TX_DATA[90] test_channels[0].chnl_tester_i.CHNL_TX_DATA[89] test_channels[0].chnl_tester_i.CHNL_TX_DATA[88] test_channels[0].chnl_tester_i.CHNL_TX_DATA[87] test_channels[0].chnl_tester_i.CHNL_TX_DATA[86] test_channels[0].chnl_tester_i.CHNL_TX_DATA[85] test_channels[0].chnl_tester_i.CHNL_TX_DATA[84] test_channels[0].chnl_tester_i.CHNL_TX_DATA[83] test_channels[0].chnl_tester_i.CHNL_TX_DATA[82] test_channels[0].chnl_tester_i.CHNL_TX_DATA[81] test_channels[0].chnl_tester_i.CHNL_TX_DATA[80] test_channels[0].chnl_tester_i.CHNL_TX_DATA[79] test_channels[0].chnl_tester_i.CHNL_TX_DATA[78] test_channels[0].chnl_tester_i.CHNL_TX_DATA[77] test_channels[0].chnl_tester_i.CHNL_TX_DATA[76] test_channels[0].chnl_tester_i.CHNL_TX_DATA[75] test_channels[0].chnl_tester_i.CHNL_TX_DATA[74] test_channels[0].chnl_tester_i.CHNL_TX_DATA[73] test_channels[0].chnl_tester_i.CHNL_TX_DATA[72] test_channels[0].chnl_tester_i.CHNL_TX_DATA[71] test_channels[0].chnl_tester_i.CHNL_TX_DATA[70] test_channels[0].chnl_tester_i.CHNL_TX_DATA[69] test_channels[0].chnl_tester_i.CHNL_TX_DATA[68] test_channels[0].chnl_tester_i.CHNL_TX_DATA[67] test_channels[0].chnl_tester_i.CHNL_TX_DATA[66] test_channels[0].chnl_tester_i.CHNL_TX_DATA[65] test_channels[0].chnl_tester_i.CHNL_TX_DATA[64] test_channels[0].chnl_tester_i.CHNL_TX_DATA[63] test_channels[0].chnl_tester_i.CHNL_TX_DATA[62] test_channels[0].chnl_tester_i.CHNL_TX_DATA[61] test_channels[0].chnl_tester_i.CHNL_TX_DATA[60] test_channels[0].chnl_tester_i.CHNL_TX_DATA[59] test_channels[0].chnl_tester_i.CHNL_TX_DATA[58] test_channels[0].chnl_tester_i.CHNL_TX_DATA[57] test_channels[0].chnl_tester_i.CHNL_TX_DATA[56] test_channels[0].chnl_tester_i.CHNL_TX_DATA[55] test_channels[0].chnl_tester_i.CHNL_TX_DATA[54] test_channels[0].chnl_tester_i.CHNL_TX_DATA[53] test_channels[0].chnl_tester_i.CHNL_TX_DATA[52] test_channels[0].chnl_tester_i.CHNL_TX_DATA[51] test_channels[0].chnl_tester_i.CHNL_TX_DATA[50] test_channels[0].chnl_tester_i.CHNL_TX_DATA[49] test_channels[0].chnl_tester_i.CHNL_TX_DATA[48] test_channels[0].chnl_tester_i.CHNL_TX_DATA[47] test_channels[0].chnl_tester_i.CHNL_TX_DATA[46] test_channels[0].chnl_tester_i.CHNL_TX_DATA[45] test_channels[0].chnl_tester_i.CHNL_TX_DATA[44] test_channels[0].chnl_tester_i.CHNL_TX_DATA[43] test_channels[0].chnl_tester_i.CHNL_TX_DATA[42] test_channels[0].chnl_tester_i.CHNL_TX_DATA[41] test_channels[0].chnl_tester_i.CHNL_TX_DATA[40] test_channels[0].chnl_tester_i.CHNL_TX_DATA[39] test_channels[0].chnl_tester_i.CHNL_TX_DATA[38] test_channels[0].chnl_tester_i.CHNL_TX_DATA[37] test_channels[0].chnl_tester_i.CHNL_TX_DATA[36] test_channels[0].chnl_tester_i.CHNL_TX_DATA[35] test_channels[0].chnl_tester_i.CHNL_TX_DATA[34] test_channels[0].chnl_tester_i.CHNL_TX_DATA[33] test_channels[0].chnl_tester_i.CHNL_TX_DATA[32] test_channels[0].chnl_tester_i.CHNL_TX_DATA[31] test_channels[0].chnl_tester_i.CHNL_TX_DATA[30] test_channels[0].chnl_tester_i.CHNL_TX_DATA[29] test_channels[0].chnl_tester_i.CHNL_TX_DATA[28] test_channels[0].chnl_tester_i.CHNL_TX_DATA[27] test_channels[0].chnl_tester_i.CHNL_TX_DATA[26] test_channels[0].chnl_tester_i.CHNL_TX_DATA[25] test_channels[0].chnl_tester_i.CHNL_TX_DATA[24] test_channels[0].chnl_tester_i.CHNL_TX_DATA[23] test_channels[0].chnl_tester_i.CHNL_TX_DATA[22] test_channels[0].chnl_tester_i.CHNL_TX_DATA[21] test_channels[0].chnl_tester_i.CHNL_TX_DATA[20] test_channels[0].chnl_tester_i.CHNL_TX_DATA[19] test_channels[0].chnl_tester_i.CHNL_TX_DATA[18] test_channels[0].chnl_tester_i.CHNL_TX_DATA[17] test_channels[0].chnl_tester_i.CHNL_TX_DATA[16] test_channels[0].chnl_tester_i.CHNL_TX_DATA[15] test_channels[0].chnl_tester_i.CHNL_TX_DATA[14] test_channels[0].chnl_tester_i.CHNL_TX_DATA[13] test_channels[0].chnl_tester_i.CHNL_TX_DATA[12] test_channels[0].chnl_tester_i.CHNL_TX_DATA[11] test_channels[0].chnl_tester_i.CHNL_TX_DATA[10] test_channels[0].chnl_tester_i.CHNL_TX_DATA[9] test_channels[0].chnl_tester_i.CHNL_TX_DATA[8] test_channels[0].chnl_tester_i.CHNL_TX_DATA[7] test_channels[0].chnl_tester_i.CHNL_TX_DATA[6] test_channels[0].chnl_tester_i.CHNL_TX_DATA[5] test_channels[0].chnl_tester_i.CHNL_TX_DATA[4] test_channels[0].chnl_tester_i.CHNL_TX_DATA[3] test_channels[0].chnl_tester_i.CHNL_TX_DATA[2] test_channels[0].chnl_tester_i.CHNL_TX_DATA[1] test_channels[0].chnl_tester_i.CHNL_TX_DATA[0]
@28
test_channels[0].chnl_tester_i.CHNL_TX_DATA_REN
test_channels[0].chnl_tester_i.CHNL_TX_DATA_VALID
test_channels[0].chnl_tester_i.CHNL_TX_LAST
@24
#{test_channels[0].chnl_tester_i.CHNL_TX_LEN[31:0]} test_channels[0].chnl_tester_i.CHNL_TX_LEN[31] test_channels[0].chnl_tester_i.CHNL_TX_LEN[30] test_channels[0].chnl_tester_i.CHNL_TX_LEN[29] test_channels[0].chnl_tester_i.CHNL_TX_LEN[28] test_channels[0].chnl_tester_i.CHNL_TX_LEN[27] test_channels[0].chnl_tester_i.CHNL_TX_LEN[26] test_channels[0].chnl_tester_i.CHNL_TX_LEN[25] test_channels[0].chnl_tester_i.CHNL_TX_LEN[24] test_channels[0].chnl_tester_i.CHNL_TX_LEN[23] test_channels[0].chnl_tester_i.CHNL_TX_LEN[22] test_channels[0].chnl_tester_i.CHNL_TX_LEN[21] test_channels[0].chnl_tester_i.CHNL_TX_LEN[20] test_channels[0].chnl_tester_i.CHNL_TX_LEN[19] test_channels[0].chnl_tester_i.CHNL_TX_LEN[18] test_channels[0].chnl_tester_i.CHNL_TX_LEN[17] test_channels[0].chnl_tester_i.CHNL_TX_LEN[16] test_channels[0].chnl_tester_i.CHNL_TX_LEN[15] test_channels[0].chnl_tester_i.CHNL_TX_LEN[14] test_channels[0].chnl_tester_i.CHNL_TX_LEN[13] test_channels[0].chnl_tester_i.CHNL_TX_LEN[12] test_channels[0].chnl_tester_i.CHNL_TX_LEN[11] test_channels[0].chnl_tester_i.CHNL_TX_LEN[10] test_channels[0].chnl_tester_i.CHNL_TX_LEN[9] test_channels[0].chnl_tester_i.CHNL_TX_LEN[8] test_channels[0].chnl_tester_i.CHNL_TX_LEN[7] test_channels[0].chnl_tester_i.CHNL_TX_LEN[6] test_channels[0].chnl_tester_i.CHNL_TX_LEN[5] test_channels[0].chnl_tester_i.CHNL_TX_LEN[4] test_channels[0].chnl_tester_i.CHNL_TX_LEN[3] test_channels[0].chnl_tester_i.CHNL_TX_LEN[2] test_channels[0].chnl_tester_i.CHNL_TX_LEN[1] test_channels[0].chnl_tester_i.CHNL_TX_LEN[0]
@22
#{test_channels[0].chnl_tester_i.CHNL_TX_OFF[30:0]} test_channels[0].chnl_tester_i.CHNL_TX_OFF[30] test_channels[0].chnl_tester_i.CHNL_TX_OFF[29] test_channels[0].chnl_tester_i.CHNL_TX_OFF[28] test_channels[0].chnl_tester_i.CHNL_TX_OFF[27] test_channels[0].chnl_tester_i.CHNL_TX_OFF[26] test_channels[0].chnl_tester_i.CHNL_TX_OFF[25] test_channels[0].chnl_tester_i.CHNL_TX_OFF[24] test_channels[0].chnl_tester_i.CHNL_TX_OFF[23] test_channels[0].chnl_tester_i.CHNL_TX_OFF[22] test_channels[0].chnl_tester_i.CHNL_TX_OFF[21] test_channels[0].chnl_tester_i.CHNL_TX_OFF[20] test_channels[0].chnl_tester_i.CHNL_TX_OFF[19] test_channels[0].chnl_tester_i.CHNL_TX_OFF[18] test_channels[0].chnl_tester_i.CHNL_TX_OFF[17] test_channels[0].chnl_tester_i.CHNL_TX_OFF[16] test_channels[0].chnl_tester_i.CHNL_TX_OFF[15] test_channels[0].chnl_tester_i.CHNL_TX_OFF[14] test_channels[0].chnl_tester_i.CHNL_TX_OFF[13] test_channels[0].chnl_tester_i.CHNL_TX_OFF[12] test_channels[0].chnl_tester_i.CHNL_TX_OFF[11] test_channels[0].chnl_tester_i.CHNL_TX_OFF[10] test_channels[0].chnl_tester_i.CHNL_TX_OFF[9] test_channels[0].chnl_tester_i.CHNL_TX_OFF[8] test_channels[0].chnl_tester_i.CHNL_TX_OFF[7] test_channels[0].chnl_tester_i.CHNL_TX_OFF[6] test_channels[0].chnl_tester_i.CHNL_TX_OFF[5] test_channels[0].chnl_tester_i.CHNL_TX_OFF[4] test_channels[0].chnl_tester_i.CHNL_TX_OFF[3] test_channels[0].chnl_tester_i.CHNL_TX_OFF[2] test_channels[0].chnl_tester_i.CHNL_TX_OFF[1] test_channels[0].chnl_tester_i.CHNL_TX_OFF[0]
@28
test_channels[0].chnl_tester_i.CLK
test_channels[0].chnl_tester_i.RST
test_channels[0].chnl_tester_i.TX_IN_PROGRESS
test_channels[0].chnl_tester_i.\rState.00
test_channels[0].chnl_tester_i.\rState.01
test_channels[0].chnl_tester_i.\tState.00
test_channels[0].chnl_tester_i.\tState.01
@24
#{test_channels[0].chnl_tester_i.rCount[31:0]} test_channels[0].chnl_tester_i.rCount[31] test_channels[0].chnl_tester_i.rCount[30] test_channels[0].chnl_tester_i.rCount[29] test_channels[0].chnl_tester_i.rCount[28] test_channels[0].chnl_tester_i.rCount[27] test_channels[0].chnl_tester_i.rCount[26] test_channels[0].chnl_tester_i.rCount[25] test_channels[0].chnl_tester_i.rCount[24] test_channels[0].chnl_tester_i.rCount[23] test_channels[0].chnl_tester_i.rCount[22] test_channels[0].chnl_tester_i.rCount[21] test_channels[0].chnl_tester_i.rCount[20] test_channels[0].chnl_tester_i.rCount[19] test_channels[0].chnl_tester_i.rCount[18] test_channels[0].chnl_tester_i.rCount[17] test_channels[0].chnl_tester_i.rCount[16] test_channels[0].chnl_tester_i.rCount[15] test_channels[0].chnl_tester_i.rCount[14] test_channels[0].chnl_tester_i.rCount[13] test_channels[0].chnl_tester_i.rCount[12] test_channels[0].chnl_tester_i.rCount[11] test_channels[0].chnl_tester_i.rCount[10] test_channels[0].chnl_tester_i.rCount[9] test_channels[0].chnl_tester_i.rCount[8] test_channels[0].chnl_tester_i.rCount[7] test_channels[0].chnl_tester_i.rCount[6] test_channels[0].chnl_tester_i.rCount[5] test_channels[0].chnl_tester_i.rCount[4] test_channels[0].chnl_tester_i.rCount[3] test_channels[0].chnl_tester_i.rCount[2] test_channels[0].chnl_tester_i.rCount[1] test_channels[0].chnl_tester_i.rCount[0]
@22
#{test_channels[0].chnl_tester_i.rData[127:0]} test_channels[0].chnl_tester_i.rData[127] test_channels[0].chnl_tester_i.rData[126] test_channels[0].chnl_tester_i.rData[125] test_channels[0].chnl_tester_i.rData[124] test_channels[0].chnl_tester_i.rData[123] test_channels[0].chnl_tester_i.rData[122] test_channels[0].chnl_tester_i.rData[121] test_channels[0].chnl_tester_i.rData[120] test_channels[0].chnl_tester_i.rData[119] test_channels[0].chnl_tester_i.rData[118] test_channels[0].chnl_tester_i.rData[117] test_channels[0].chnl_tester_i.rData[116] test_channels[0].chnl_tester_i.rData[115] test_channels[0].chnl_tester_i.rData[114] test_channels[0].chnl_tester_i.rData[113] test_channels[0].chnl_tester_i.rData[112] test_channels[0].chnl_tester_i.rData[111] test_channels[0].chnl_tester_i.rData[110] test_channels[0].chnl_tester_i.rData[109] test_channels[0].chnl_tester_i.rData[108] test_channels[0].chnl_tester_i.rData[107] test_channels[0].chnl_tester_i.rData[106] test_channels[0].chnl_tester_i.rData[105] test_channels[0].chnl_tester_i.rData[104] test_channels[0].chnl_tester_i.rData[103] test_channels[0].chnl_tester_i.rData[102] test_channels[0].chnl_tester_i.rData[101] test_channels[0].chnl_tester_i.rData[100] test_channels[0].chnl_tester_i.rData[99] test_channels[0].chnl_tester_i.rData[98] test_channels[0].chnl_tester_i.rData[97] test_channels[0].chnl_tester_i.rData[96] test_channels[0].chnl_tester_i.rData[95] test_channels[0].chnl_tester_i.rData[94] test_channels[0].chnl_tester_i.rData[93] test_channels[0].chnl_tester_i.rData[92] test_channels[0].chnl_tester_i.rData[91] test_channels[0].chnl_tester_i.rData[90] test_channels[0].chnl_tester_i.rData[89] test_channels[0].chnl_tester_i.rData[88] test_channels[0].chnl_tester_i.rData[87] test_channels[0].chnl_tester_i.rData[86] test_channels[0].chnl_tester_i.rData[85] test_channels[0].chnl_tester_i.rData[84] test_channels[0].chnl_tester_i.rData[83] test_channels[0].chnl_tester_i.rData[82] test_channels[0].chnl_tester_i.rData[81] test_channels[0].chnl_tester_i.rData[80] test_channels[0].chnl_tester_i.rData[79] test_channels[0].chnl_tester_i.rData[78] test_channels[0].chnl_tester_i.rData[77] test_channels[0].chnl_tester_i.rData[76] test_channels[0].chnl_tester_i.rData[75] test_channels[0].chnl_tester_i.rData[74] test_channels[0].chnl_tester_i.rData[73] test_channels[0].chnl_tester_i.rData[72] test_channels[0].chnl_tester_i.rData[71] test_channels[0].chnl_tester_i.rData[70] test_channels[0].chnl_tester_i.rData[69] test_channels[0].chnl_tester_i.rData[68] test_channels[0].chnl_tester_i.rData[67] test_channels[0].chnl_tester_i.rData[66] test_channels[0].chnl_tester_i.rData[65] test_channels[0].chnl_tester_i.rData[64] test_channels[0].chnl_tester_i.rData[63] test_channels[0].chnl_tester_i.rData[62] test_channels[0].chnl_tester_i.rData[61] test_channels[0].chnl_tester_i.rData[60] test_channels[0].chnl_tester_i.rData[59] test_channels[0].chnl_tester_i.rData[58] test_channels[0].chnl_tester_i.rData[57] test_channels[0].chnl_tester_i.rData[56] test_channels[0].chnl_tester_i.rData[55] test_channels[0].chnl_tester_i.rData[54] test_channels[0].chnl_tester_i.rData[53] test_channels[0].chnl_tester_i.rData[52] test_channels[0].chnl_tester_i.rData[51] test_channels[0].chnl_tester_i.rData[50] test_channels[0].chnl_tester_i.rData[49] test_channels[0].chnl_tester_i.rData[48] test_channels[0].chnl_tester_i.rData[47] test_channels[0].chnl_tester_i.rData[46] test_channels[0].chnl_tester_i.rData[45] test_channels[0].chnl_tester_i.rData[44] test_channels[0].chnl_tester_i.rData[43] test_channels[0].chnl_tester_i.rData[42] test_channels[0].chnl_tester_i.rData[41] test_channels[0].chnl_tester_i.rData[40] test_channels[0].chnl_tester_i.rData[39] test_channels[0].chnl_tester_i.rData[38] test_channels[0].chnl_tester_i.rData[37] test_channels[0].chnl_tester_i.rData[36] test_channels[0].chnl_tester_i.rData[35] test_channels[0].chnl_tester_i.rData[34] test_channels[0].chnl_tester_i.rData[33] test_channels[0].chnl_tester_i.rData[32] test_channels[0].chnl_tester_i.rData[31] test_channels[0].chnl_tester_i.rData[30] test_channels[0].chnl_tester_i.rData[29] test_channels[0].chnl_tester_i.rData[28] test_channels[0].chnl_tester_i.rData[27] test_channels[0].chnl_tester_i.rData[26] test_channels[0].chnl_tester_i.rData[25] test_channels[0].chnl_tester_i.rData[24] test_channels[0].chnl_tester_i.rData[23] test_channels[0].chnl_tester_i.rData[22] test_channels[0].chnl_tester_i.rData[21] test_channels[0].chnl_tester_i.rData[20] test_channels[0].chnl_tester_i.rData[19] test_channels[0].chnl_tester_i.rData[18] test_channels[0].chnl_tester_i.rData[17] test_channels[0].chnl_tester_i.rData[16] test_channels[0].chnl_tester_i.rData[15] test_channels[0].chnl_tester_i.rData[14] test_channels[0].chnl_tester_i.rData[13] test_channels[0].chnl_tester_i.rData[12] test_channels[0].chnl_tester_i.rData[11] test_channels[0].chnl_tester_i.rData[10] test_channels[0].chnl_tester_i.rData[9] test_channels[0].chnl_tester_i.rData[8] test_channels[0].chnl_tester_i.rData[7] test_channels[0].chnl_tester_i.rData[6] test_channels[0].chnl_tester_i.rData[5] test_channels[0].chnl_tester_i.rData[4] test_channels[0].chnl_tester_i.rData[3] test_channels[0].chnl_tester_i.rData[2] test_channels[0].chnl_tester_i.rData[1] test_channels[0].chnl_tester_i.rData[0]
@24
#{test_channels[0].chnl_tester_i.tCount[31:0]} test_channels[0].chnl_tester_i.tCount[31] test_channels[0].chnl_tester_i.tCount[30] test_channels[0].chnl_tester_i.tCount[29] test_channels[0].chnl_tester_i.tCount[28] test_channels[0].chnl_tester_i.tCount[27] test_channels[0].chnl_tester_i.tCount[26] test_channels[0].chnl_tester_i.tCount[25] test_channels[0].chnl_tester_i.tCount[24] test_channels[0].chnl_tester_i.tCount[23] test_channels[0].chnl_tester_i.tCount[22] test_channels[0].chnl_tester_i.tCount[21] test_channels[0].chnl_tester_i.tCount[20] test_channels[0].chnl_tester_i.tCount[19] test_channels[0].chnl_tester_i.tCount[18] test_channels[0].chnl_tester_i.tCount[17] test_channels[0].chnl_tester_i.tCount[16] test_channels[0].chnl_tester_i.tCount[15] test_channels[0].chnl_tester_i.tCount[14] test_channels[0].chnl_tester_i.tCount[13] test_channels[0].chnl_tester_i.tCount[12] test_channels[0].chnl_tester_i.tCount[11] test_channels[0].chnl_tester_i.tCount[10] test_channels[0].chnl_tester_i.tCount[9] test_channels[0].chnl_tester_i.tCount[8] test_channels[0].chnl_tester_i.tCount[7] test_channels[0].chnl_tester_i.tCount[6] test_channels[0].chnl_tester_i.tCount[5] test_channels[0].chnl_tester_i.tCount[4] test_channels[0].chnl_tester_i.tCount[3] test_channels[0].chnl_tester_i.tCount[2] test_channels[0].chnl_tester_i.tCount[1] test_channels[0].chnl_tester_i.tCount[0]
@28
riffa.riffa_inst.channels[0].channel.channel.txPort.gate.\rState.00
riffa.riffa_inst.channels[0].channel.channel.txPort.gate.\rState.01
riffa.riffa_inst.channels[0].channel.channel.txPort.gate.\rState.10
riffa.riffa_inst.channels[0].channel.channel.txPort.gate.\rState.11
riffa.riffa_inst.channels[0].channel.channel.txPort.gate.rChnlTx
@22
#{riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[128:0]} riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[128] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[127] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[126] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[125] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[124] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[123] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[122] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[121] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[120] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[119] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[118] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[117] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[116] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[115] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[114] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[113] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[112] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[111] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[110] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[109] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[108] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[107] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[106] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[105] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[104] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[103] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[102] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[101] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[100] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[99] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[98] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[97] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[96] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[95] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[94] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[93] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[92] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[91] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[90] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[89] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[88] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[87] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[86] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[85] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[84] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[83] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[82] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[81] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[80] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[79] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[78] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[77] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[76] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[75] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[74] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[73] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[72] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[71] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[70] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[69] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[68] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[67] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[66] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[65] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[64] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[63] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[62] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[61] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[60] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[59] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[58] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[57] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[56] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[55] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[54] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[53] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[52] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[51] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[50] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[49] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[48] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[47] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[46] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[45] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[44] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[43] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[42] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[41] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[40] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[39] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[38] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[37] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[36] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[35] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[34] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[33] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[32] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[31] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[30] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[29] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[28] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[27] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[26] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[25] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[24] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[23] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[22] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[21] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[20] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[19] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[18] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[17] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[16] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[15] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[14] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[13] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[12] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[11] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[10] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[9] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[8] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[7] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[6] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[5] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[4] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[3] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[2] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[1] riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_DATA[0]
@28
riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_EMPTY
riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.RD_EN
riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.WR_EN
riffa.riffa_inst.channels[0].channel.channel.txPort.gate.fifo.WR_FULL
riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.ACK
@22
#{riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[31:0]} riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[31] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[30] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[29] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[28] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[27] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[26] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[25] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[24] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[23] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[22] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[21] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[20] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[19] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[18] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[17] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[16] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[15] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[14] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[13] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[12] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[11] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[10] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[9] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[8] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[7] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[6] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[5] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[4] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[3] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[2] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[1] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.LEN[0]
@28
riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.TX_ERR
riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rAlmostAllRecvd
riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rAlmostFull
riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rDataValid[0]
riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rEvent
riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rLenEQ0Hi
riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rLenLE4Lo
@22
#{riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rState[5:0]} riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rState[5] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rState[4] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rState[3] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rState[2] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rState[1] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rState[0]
#{riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[31:0]} riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[31] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[30] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[29] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[28] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[27] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[26] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[25] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[24] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[23] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[22] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[21] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[20] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[19] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[18] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[17] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[16] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[15] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[14] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[13] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[12] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[11] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[10] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[9] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[8] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[7] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[6] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[5] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[4] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[3] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[2] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[1] riffa.riffa_inst.channels[0].channel.channel.txPort.monitor.rWordsRecvdAdv[0]
@28
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.TXR_META_READY
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.WR_DATA_REN[0]
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapAddr64
@22
#{riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapChnl[3:0]} riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapChnl[3] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapChnl[2] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapChnl[1] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapChnl[0]
@28
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapIsWr
@22
#{riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[9:0]} riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[9] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[8] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[7] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[6] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[5] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[4] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[3] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[2] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[1] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapLen[0]
#{riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapState[3:0]} riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapState[3] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapState[2] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapState[1] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCapState[0]
@28
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rCountDone
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rIsWr
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rMainState
@22
#{riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rRdChnl[3:0]} riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rRdChnl[3] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rRdChnl[2] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rRdChnl[1] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rRdChnl[0]
#{riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rWrChnl[3:0]} riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rWrChnl[3] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rWrChnl[2] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rWrChnl[1] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.rWrChnl[0]
@28
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.wRdAck
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.selWr.REQ
riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.selWr.REQ_ALL[0]
@22
#{riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.selWr.rReqChnl[3:0]} riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.selWr.rReqChnl[3] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.selWr.rReqChnl[2] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.selWr.rReqChnl[1] riffa.riffa_inst.tx_mux_inst.tx_mux_128_inst.selWr.rReqChnl[0]
@28
riffa.riffa_inst.channels[0].channel.channel.txPort.writer.SG_ELEM_RDY
@22
#{riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[31:0]} riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[31] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[30] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[29] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[28] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[27] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[26] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[25] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[24] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[23] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[22] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[21] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[20] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[19] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[18] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[17] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[16] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[15] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[14] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[13] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[12] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[11] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[10] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[9] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[8] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[7] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[6] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[5] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[4] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[3] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[2] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[1] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rDoneLen[0]
#{riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rMainState[7:0]} riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rMainState[7] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rMainState[6] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rMainState[5] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rMainState[4] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rMainState[3] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rMainState[2] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rMainState[1] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rMainState[0]
@28
riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rNotRequesting
@22
#{riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[31:0]} riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[31] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[30] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[29] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[28] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[27] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[26] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[25] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[24] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[23] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[22] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[21] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[20] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[19] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[18] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[17] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[16] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[15] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[14] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[13] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[12] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[11] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[10] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[9] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[8] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[7] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[6] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[5] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[4] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[3] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[2] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[1] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rOffLast[0]
@28
riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rStarted
riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxErrd
riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxReqAck
@22
#{riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxState[7:0]} riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxState[7] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxState[6] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxState[5] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxState[4] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxState[3] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxState[2] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxState[1] riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rTxState[0]
@28
riffa.riffa_inst.channels[0].channel.channel.txPort.writer.rWordsEQ0
riffa.riffa_inst.channels[0].channel.channel.txPort.sgListReader.BUF_DATA_EMPTY
riffa.riffa_inst.channels[0].channel.channel.txPort.sgListReader.BUF_DATA_REN
riffa.riffa_inst.channels[0].channel.channel.txPort.sgListReader.REN
riffa.riffa_inst.channels[0].channel.channel.txPort.sgListReader.rCapState
riffa.riffa_inst.channels[0].channel.channel.txPort.sgListReader.rDataValid
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.DATA_IN_EN[2:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.DATA_IN_EN[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.DATA_IN_EN[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.DATA_IN_EN[0]
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.PACKED_WEN
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.rDataMaskedEn[2:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.rDataMaskedEn[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.rDataMaskedEn[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.rDataMaskedEn[0]
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.rPackedCount[2:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.rPackedCount[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.rPackedCount[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.rPackedCount[0]
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxFifoPacker.rPackedFlush
riffa.riffa_inst.intr.INTR_MSI_RDY
riffa.riffa_inst.intr.INTR_MSI_REQUEST
riffa.riffa_inst.intr.RX_SG_BUF_RECVD[0]
riffa.riffa_inst.intr.RX_TXN_DONE[0]
riffa.riffa_inst.intr.TX_SG_BUF_RECVD[0]
riffa.riffa_inst.intr.TX_TXN[0]
riffa.riffa_inst.intr.TX_TXN_DONE[0]
@22
#{riffa.riffa_inst.intr.VECT_0[31:0]} riffa.riffa_inst.intr.VECT_0[31] riffa.riffa_inst.intr.VECT_0[30] riffa.riffa_inst.intr.VECT_0[29] riffa.riffa_inst.intr.VECT_0[28] riffa.riffa_inst.intr.VECT_0[27] riffa.riffa_inst.intr.VECT_0[26] riffa.riffa_inst.intr.VECT_0[25] riffa.riffa_inst.intr.VECT_0[24] riffa.riffa_inst.intr.VECT_0[23] riffa.riffa_inst.intr.VECT_0[22] riffa.riffa_inst.intr.VECT_0[21] riffa.riffa_inst.intr.VECT_0[20] riffa.riffa_inst.intr.VECT_0[19] riffa.riffa_inst.intr.VECT_0[18] riffa.riffa_inst.intr.VECT_0[17] riffa.riffa_inst.intr.VECT_0[16] riffa.riffa_inst.intr.VECT_0[15] riffa.riffa_inst.intr.VECT_0[14] riffa.riffa_inst.intr.VECT_0[13] riffa.riffa_inst.intr.VECT_0[12] riffa.riffa_inst.intr.VECT_0[11] riffa.riffa_inst.intr.VECT_0[10] riffa.riffa_inst.intr.VECT_0[9] riffa.riffa_inst.intr.VECT_0[8] riffa.riffa_inst.intr.VECT_0[7] riffa.riffa_inst.intr.VECT_0[6] riffa.riffa_inst.intr.VECT_0[5] riffa.riffa_inst.intr.VECT_0[4] riffa.riffa_inst.intr.VECT_0[3] riffa.riffa_inst.intr.VECT_0[2] riffa.riffa_inst.intr.VECT_0[1] riffa.riffa_inst.intr.VECT_0[0]
@28
riffa.riffa_inst.intr.VECT_0_RST
@22
#{riffa.riffa_inst.intr.VECT_1[31:0]} riffa.riffa_inst.intr.VECT_1[31] riffa.riffa_inst.intr.VECT_1[30] riffa.riffa_inst.intr.VECT_1[29] riffa.riffa_inst.intr.VECT_1[28] riffa.riffa_inst.intr.VECT_1[27] riffa.riffa_inst.intr.VECT_1[26] riffa.riffa_inst.intr.VECT_1[25] riffa.riffa_inst.intr.VECT_1[24] riffa.riffa_inst.intr.VECT_1[23] riffa.riffa_inst.intr.VECT_1[22] riffa.riffa_inst.intr.VECT_1[21] riffa.riffa_inst.intr.VECT_1[20] riffa.riffa_inst.intr.VECT_1[19] riffa.riffa_inst.intr.VECT_1[18] riffa.riffa_inst.intr.VECT_1[17] riffa.riffa_inst.intr.VECT_1[16] riffa.riffa_inst.intr.VECT_1[15] riffa.riffa_inst.intr.VECT_1[14] riffa.riffa_inst.intr.VECT_1[13] riffa.riffa_inst.intr.VECT_1[12] riffa.riffa_inst.intr.VECT_1[11] riffa.riffa_inst.intr.VECT_1[10] riffa.riffa_inst.intr.VECT_1[9] riffa.riffa_inst.intr.VECT_1[8] riffa.riffa_inst.intr.VECT_1[7] riffa.riffa_inst.intr.VECT_1[6] riffa.riffa_inst.intr.VECT_1[5] riffa.riffa_inst.intr.VECT_1[4] riffa.riffa_inst.intr.VECT_1[3] riffa.riffa_inst.intr.VECT_1[2] riffa.riffa_inst.intr.VECT_1[1] riffa.riffa_inst.intr.VECT_1[0]
@28
riffa.riffa_inst.intr.VECT_1_RST
@22
#{riffa.riffa_inst.intr.VECT_RST[31:0]} riffa.riffa_inst.intr.VECT_RST[31] riffa.riffa_inst.intr.VECT_RST[30] riffa.riffa_inst.intr.VECT_RST[29] riffa.riffa_inst.intr.VECT_RST[28] riffa.riffa_inst.intr.VECT_RST[27] riffa.riffa_inst.intr.VECT_RST[26] riffa.riffa_inst.intr.VECT_RST[25] riffa.riffa_inst.intr.VECT_RST[24] riffa.riffa_inst.intr.VECT_RST[23] riffa.riffa_inst.intr.VECT_RST[22] riffa.riffa_inst.intr.VECT_RST[21] riffa.riffa_inst.intr.VECT_RST[20] riffa.riffa_inst.intr.VECT_RST[19] riffa.riffa_inst.intr.VECT_RST[18] riffa.riffa_inst.intr.VECT_RST[17] riffa.riffa_inst.intr.VECT_RST[16] riffa.riffa_inst.intr.VECT_RST[15] riffa.riffa_inst.intr.VECT_RST[14] riffa.riffa_inst.intr.VECT_RST[13] riffa.riffa_inst.intr.VECT_RST[12] riffa.riffa_inst.intr.VECT_RST[11] riffa.riffa_inst.intr.VECT_RST[10] riffa.riffa_inst.intr.VECT_RST[9] riffa.riffa_inst.intr.VECT_RST[8] riffa.riffa_inst.intr.VECT_RST[7] riffa.riffa_inst.intr.VECT_RST[6] riffa.riffa_inst.intr.VECT_RST[5] riffa.riffa_inst.intr.VECT_RST[4] riffa.riffa_inst.intr.VECT_RST[3] riffa.riffa_inst.intr.VECT_RST[2] riffa.riffa_inst.intr.VECT_RST[1] riffa.riffa_inst.intr.VECT_RST[0]
#{riffa.riffa_inst.intr.rVect0[31:0]} riffa.riffa_inst.intr.rVect0[31] riffa.riffa_inst.intr.rVect0[30] riffa.riffa_inst.intr.rVect0[29] riffa.riffa_inst.intr.rVect0[28] riffa.riffa_inst.intr.rVect0[27] riffa.riffa_inst.intr.rVect0[26] riffa.riffa_inst.intr.rVect0[25] riffa.riffa_inst.intr.rVect0[24] riffa.riffa_inst.intr.rVect0[23] riffa.riffa_inst.intr.rVect0[22] riffa.riffa_inst.intr.rVect0[21] riffa.riffa_inst.intr.rVect0[20] riffa.riffa_inst.intr.rVect0[19] riffa.riffa_inst.intr.rVect0[18] riffa.riffa_inst.intr.rVect0[17] riffa.riffa_inst.intr.rVect0[16] riffa.riffa_inst.intr.rVect0[15] riffa.riffa_inst.intr.rVect0[14] riffa.riffa_inst.intr.rVect0[13] riffa.riffa_inst.intr.rVect0[12] riffa.riffa_inst.intr.rVect0[11] riffa.riffa_inst.intr.rVect0[10] riffa.riffa_inst.intr.rVect0[9] riffa.riffa_inst.intr.rVect0[8] riffa.riffa_inst.intr.rVect0[7] riffa.riffa_inst.intr.rVect0[6] riffa.riffa_inst.intr.rVect0[5] riffa.riffa_inst.intr.rVect0[4] riffa.riffa_inst.intr.rVect0[3] riffa.riffa_inst.intr.rVect0[2] riffa.riffa_inst.intr.rVect0[1] riffa.riffa_inst.intr.rVect0[0]
#{riffa.riffa_inst.intr.rVect1[31:0]} riffa.riffa_inst.intr.rVect1[31] riffa.riffa_inst.intr.rVect1[30] riffa.riffa_inst.intr.rVect1[29] riffa.riffa_inst.intr.rVect1[28] riffa.riffa_inst.intr.rVect1[27] riffa.riffa_inst.intr.rVect1[26] riffa.riffa_inst.intr.rVect1[25] riffa.riffa_inst.intr.rVect1[24] riffa.riffa_inst.intr.rVect1[23] riffa.riffa_inst.intr.rVect1[22] riffa.riffa_inst.intr.rVect1[21] riffa.riffa_inst.intr.rVect1[20] riffa.riffa_inst.intr.rVect1[19] riffa.riffa_inst.intr.rVect1[18] riffa.riffa_inst.intr.rVect1[17] riffa.riffa_inst.intr.rVect1[16] riffa.riffa_inst.intr.rVect1[15] riffa.riffa_inst.intr.rVect1[14] riffa.riffa_inst.intr.rVect1[13] riffa.riffa_inst.intr.rVect1[12] riffa.riffa_inst.intr.rVect1[11] riffa.riffa_inst.intr.rVect1[10] riffa.riffa_inst.intr.rVect1[9] riffa.riffa_inst.intr.rVect1[8] riffa.riffa_inst.intr.rVect1[7] riffa.riffa_inst.intr.rVect1[6] riffa.riffa_inst.intr.rVect1[5] riffa.riffa_inst.intr.rVect1[4] riffa.riffa_inst.intr.rVect1[3] riffa.riffa_inst.intr.rVect1[2] riffa.riffa_inst.intr.rVect1[1] riffa.riffa_inst.intr.rVect1[0]
@28
riffa.riffa_inst.intr.intrCtlr.INTR
riffa.riffa_inst.intr.intrCtlr.INTR_DONE
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_ADDR_HI_VALID
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_ADDR_LO_VALID
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[31:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[31] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[30] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[29] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[28] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[27] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[26] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[25] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[24] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[23] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[22] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[21] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[20] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[19] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[18] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[17] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[16] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[15] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[14] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[13] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[12] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[11] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[10] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_LEN_VALID
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_RECVD
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.CONFIG_MAX_READ_REQUEST_SIZE[2:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.CONFIG_MAX_READ_REQUEST_SIZE[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.CONFIG_MAX_READ_REQUEST_SIZE[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.CONFIG_MAX_READ_REQUEST_SIZE[0]
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[10:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[10] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_FLUSH
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_FLUSHED
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_RST
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RST
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[63:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[63] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[62] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[61] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[60] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[59] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[58] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[57] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[56] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[55] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[54] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[53] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[52] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[51] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[50] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[49] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[48] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[47] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[46] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[45] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[44] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[43] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[42] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[41] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[40] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[39] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[38] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[37] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[36] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[35] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[34] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[33] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[32] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[31] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[30] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[29] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[28] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[27] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[26] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[25] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[24] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[23] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[22] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[21] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[20] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[19] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[18] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[17] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[16] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[15] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[14] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[13] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[12] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[11] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[10] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_DONE
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[9:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_REQ
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_REQ_ACK
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.USER_RST
@25
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[7:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_ADDR_HI_VALID
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_ADDR_LO_VALID
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[31:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[31] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[30] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[29] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[28] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[27] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[26] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[25] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[24] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[23] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[22] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[21] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[20] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[19] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[18] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[17] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[16] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[15] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[14] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[13] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[12] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[11] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[10] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_DATA[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_LEN_VALID
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.BUF_RECVD
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.CONFIG_MAX_READ_REQUEST_SIZE[2:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.CONFIG_MAX_READ_REQUEST_SIZE[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.CONFIG_MAX_READ_REQUEST_SIZE[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.CONFIG_MAX_READ_REQUEST_SIZE[0]
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[10:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[10] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_COUNT[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_FLUSH
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_FLUSHED
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.FIFO_RST
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[63:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[63] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[62] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[61] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[60] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[59] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[58] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[57] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[56] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[55] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[54] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[53] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[52] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[51] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[50] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[49] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[48] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[47] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[46] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[45] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[44] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[43] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[42] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[41] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[40] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[39] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[38] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[37] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[36] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[35] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[34] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[33] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[32] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[31] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[30] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[29] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[28] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[27] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[26] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[25] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[24] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[23] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[22] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[21] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[20] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[19] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[18] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[17] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[16] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[15] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[14] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[13] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[12] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[11] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[10] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_ADDR[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_DONE
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[9:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_LEN[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_REQ
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.RX_REQ_ACK
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.USER_RST
@25
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.rState[7:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.rState[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.rState[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.rState[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.rState[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.rState[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.rState[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.rState[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgRxReq.rState[0]
@22
#{riffa.riffa_inst.reg_inst.field_demux.RD_DATA[15:0]} riffa.riffa_inst.reg_inst.field_demux.RD_DATA[15] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[14] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[13] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[12] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[11] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[10] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[9] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[8] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[7] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[6] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[5] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[4] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[3] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[2] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[1] riffa.riffa_inst.reg_inst.field_demux.RD_DATA[0]
@28
riffa.riffa_inst.reg_inst.field_demux.WR_DATA[0]
@23
#{riffa.riffa_inst.reg_inst.field_demux.WR_SEL[3:0]} riffa.riffa_inst.reg_inst.field_demux.WR_SEL[3] riffa.riffa_inst.reg_inst.field_demux.WR_SEL[2] riffa.riffa_inst.reg_inst.field_demux.WR_SEL[1] riffa.riffa_inst.reg_inst.field_demux.WR_SEL[0]
@28
riffa.riffa_inst.reg_inst.tx_len_ready_demux.WR_SEL[0]
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.DONE_RXR_RST
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RST_BUS
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RST_LOGIC
@22
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[127:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[127] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[126] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[125] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[124] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[123] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[122] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[121] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[120] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[119] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[118] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[117] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[116] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[115] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[114] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[113] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[112] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[111] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[110] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[109] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[108] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[107] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[106] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[105] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[104] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[103] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[102] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[101] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[100] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[99] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[98] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[97] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[96] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[95] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[94] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[93] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[92] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[91] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[90] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[89] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[88] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[87] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[86] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[85] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[84] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[83] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[82] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[81] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[80] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[79] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[78] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[77] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[76] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[75] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[74] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[73] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[72] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[71] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[70] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[69] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[68] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[67] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[66] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[65] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[64] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[63] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[62] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[61] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[60] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[59] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[58] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[57] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[56] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[55] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[54] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[53] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[52] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[51] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[50] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[49] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[48] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[47] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[46] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[45] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[44] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[43] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[42] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[41] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[40] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[39] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[38] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[37] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[36] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[35] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[34] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[33] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[32] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[31] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[30] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[29] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[28] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[27] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[26] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[25] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[24] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[23] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[22] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[21] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[20] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[19] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[18] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[17] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[16] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[15] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[14] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[13] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[12] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[11] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[10] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[9] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[8] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA[0]
@29
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_END_FLAG
@28
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_END_OFFSET[1:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_END_OFFSET[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_END_OFFSET[0]
@29
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_START_FLAG
@28
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_START_OFFSET[1:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_START_OFFSET[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_START_OFFSET[0]
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_VALID
@22
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_WORD_ENABLE[3:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_WORD_ENABLE[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_WORD_ENABLE[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_WORD_ENABLE[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_DATA_WORD_ENABLE[0]
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[63:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[63] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[62] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[61] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[60] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[59] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[58] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[57] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[56] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[55] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[54] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[53] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[52] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[51] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[50] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[49] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[48] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[47] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[46] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[45] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[44] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[43] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[42] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[41] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[40] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[39] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[38] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[37] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[36] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[35] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[34] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[33] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[32] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[31] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[30] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[29] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[28] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[27] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[26] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[25] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[24] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[23] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[22] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[21] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[20] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[19] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[18] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[17] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[16] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[15] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[14] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[13] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[12] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[11] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[10] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[9] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[8] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ADDR[0]
@28
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ATTR[2:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ATTR[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ATTR[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_ATTR[0]
@22
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_BAR_DECODED[7:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_BAR_DECODED[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_BAR_DECODED[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_BAR_DECODED[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_BAR_DECODED[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_BAR_DECODED[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_BAR_DECODED[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_BAR_DECODED[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_BAR_DECODED[0]
@28
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_EP
@23
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_FDWBE[3:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_FDWBE[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_FDWBE[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_FDWBE[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_FDWBE[0]
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LDWBE[3:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LDWBE[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LDWBE[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LDWBE[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LDWBE[0]
@22
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[9:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[9] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[8] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_LENGTH[0]
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[15:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[15] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[14] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[13] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[12] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[11] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[10] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[9] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[8] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_REQUESTER_ID[0]
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TAG[7:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TAG[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TAG[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TAG[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TAG[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TAG[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TAG[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TAG[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TAG[0]
@28
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TC[2:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TC[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TC[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TC[0]
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TYPE[2:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TYPE[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TYPE[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RXR_META_TYPE[0]
@22
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[639:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[639] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[638] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[637] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[636] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[635] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[634] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[633] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[632] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[631] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[630] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[629] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[628] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[627] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[626] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[625] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[624] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[623] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[622] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[621] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[620] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[619] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[618] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[617] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[616] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[615] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[614] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[613] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[612] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[611] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[610] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[609] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[608] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[607] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[606] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[605] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[604] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[603] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[602] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[601] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[600] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[599] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[598] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[597] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[596] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[595] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[594] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[593] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[592] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[591] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[590] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[589] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[588] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[587] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[586] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[585] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[584] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[583] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[582] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[581] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[580] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[579] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[578] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[577] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[576] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[575] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[574] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[573] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[572] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[571] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[570] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[569] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[568] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[567] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[566] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[565] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[564] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[563] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[562] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[561] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[560] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[559] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[558] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[557] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[556] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[555] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[554] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[553] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[552] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[551] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[550] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[549] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[548] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[547] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[546] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[545] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[544] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[543] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[542] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[541] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[540] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[539] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[538] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[537] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[536] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[535] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[534] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[533] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[532] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[531] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[530] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[529] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[528] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[527] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[526] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[525] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[524] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[523] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[522] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[521] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[520] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[519] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[518] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[517] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[516] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[515] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[514] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[513] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[512] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[511] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[510] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[509] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[508] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[507] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[506] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[505] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[504] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[503] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[502] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[501] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[500] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[499] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[498] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[497] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[496] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[495] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[494] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[493] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[492] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[491] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[490] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[489] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[488] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[487] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[486] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[485] 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riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[52] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[51] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[50] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[49] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[48] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[47] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[46] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[45] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[44] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[43] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[42] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[41] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[40] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[39] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[38] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[37] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[36] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[35] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[34] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[33] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[32] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[31] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[30] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[29] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[28] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[27] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[26] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[25] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[24] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[23] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[22] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[21] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[20] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[19] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[18] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[17] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[16] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[15] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[14] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[13] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[12] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[11] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[10] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[9] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[8] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_DATA[0]
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[19:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[19] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[18] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[17] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[16] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[15] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[14] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[13] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[12] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[11] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[10] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[9] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[8] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_END_OFFSET[0]
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_EOP[4:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_EOP[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_EOP[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_EOP[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_EOP[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_EOP[0]
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_SOP[4:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_SOP[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_SOP[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_SOP[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_SOP[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_SOP[0]
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_VALID[4:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_VALID[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_VALID[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_VALID[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_VALID[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_SR_VALID[0]
@23
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[127:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[127] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[126] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[125] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[124] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[123] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[122] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[121] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[120] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[119] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[118] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[117] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[116] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[115] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[114] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[113] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[112] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[111] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[110] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[109] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[108] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[107] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[106] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[105] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[104] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[103] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[102] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[101] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[100] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[99] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[98] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[97] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[96] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[95] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[94] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[93] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[92] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[91] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[90] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[89] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[88] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[87] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[86] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[85] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[84] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[83] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[82] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[81] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[80] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[79] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[78] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[77] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[76] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[75] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[74] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[73] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[72] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[71] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[70] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[69] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[68] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[67] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[66] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[65] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[64] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[63] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[62] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[61] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[60] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[59] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[58] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[57] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[56] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[55] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[54] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[53] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[52] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[51] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[50] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[49] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[48] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[47] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[46] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[45] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[44] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[43] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[42] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[41] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[40] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[39] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[38] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[37] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[36] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[35] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[34] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[33] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[32] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[31] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[30] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[29] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[28] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[27] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[26] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[25] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[24] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[23] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[22] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[21] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[20] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[19] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[18] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[17] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[16] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[15] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[14] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[13] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[12] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[11] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[10] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[9] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[8] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP[0]
@22
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_BAR_DECODE[7:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_BAR_DECODE[7] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_BAR_DECODE[6] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_BAR_DECODE[5] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_BAR_DECODE[4] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_BAR_DECODE[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_BAR_DECODE[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_BAR_DECODE[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_BAR_DECODE[0]
@29
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_END_FLAG
@22
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_END_OFFSET[3:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_END_OFFSET[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_END_OFFSET[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_END_OFFSET[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_END_OFFSET[0]
@29
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_START_FLAG
@22
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_START_OFFSET[3:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_START_OFFSET[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_START_OFFSET[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_START_OFFSET[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_START_OFFSET[0]
@29
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.RX_TLP_VALID
@28
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.rValid
riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wEndFlag
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wRxSrSop[2:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wRxSrSop[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wRxSrSop[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wRxSrSop[0]
@22
#{riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wStartFlags[3:0]} riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wStartFlags[3] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wStartFlags[2] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wStartFlags[1] riffa.engine_layer_inst.rx_engine_classic_inst.rxr_engine_inst.wStartFlags[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_ADDR_HI_VALID
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_ADDR_LO_VALID
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[31:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[31] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[30] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[29] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[28] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[27] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[26] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[25] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[24] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[23] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[22] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[21] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[20] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[19] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[18] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[17] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[16] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[15] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[14] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[13] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[12] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[11] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[10] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_DATA[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_LEN_VALID
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.BUF_RECVD
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.CONFIG_MAX_READ_REQUEST_SIZE[2:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.CONFIG_MAX_READ_REQUEST_SIZE[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.CONFIG_MAX_READ_REQUEST_SIZE[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.CONFIG_MAX_READ_REQUEST_SIZE[0]
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[10:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[10] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_COUNT[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_FLUSH
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_FLUSHED
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.FIFO_RST
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RST
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[63:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[63] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[62] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[61] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[60] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[59] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[58] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[57] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[56] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[55] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[54] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[53] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[52] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[51] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[50] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[49] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[48] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[47] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[46] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[45] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[44] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[43] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[42] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[41] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[40] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[39] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[38] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[37] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[36] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[35] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[34] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[33] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[32] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[31] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[30] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[29] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[28] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[27] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[26] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[25] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[24] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[23] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[22] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[21] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[20] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[19] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[18] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[17] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[16] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[15] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[14] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[13] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[12] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[11] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[10] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_ADDR[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_DONE
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[9:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[9] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[8] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_LEN[0]
@28
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_REQ
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.RX_REQ_ACK
riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.USER_RST
@22
#{riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[7:0]} riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[7] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[6] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[5] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[4] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[3] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[2] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[1] riffa.riffa_inst.channels[0].channel.channel.rxPort.sgTxReq.rState[0]
[pattern_trace] 1
[pattern_trace] 0

riffa_full_duplex.vcd

$comment
Copyright (C) 2017  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.
$end

$date 
  08/03/2018 18:48:04 
$end
$version 
 QUARTUS_VCD_EXPORT 1.0 
$end
$timescale
  1 ps
$end
$scope module test_channels[0].chnl_tester_i $end
$var reg 1 ! CLK $end
$var reg 1 " CHNL_RX $end
$var reg 1 # CHNL_RX_ACK $end
$var reg 1 $ CHNL_RX_CLK $end
$var reg 1 % CHNL_RX_DATA_REN $end
$var reg 1 & CHNL_RX_DATA_VALID $end
$var reg 1 ' CHNL_RX_LAST $end
$var reg 1 ( CHNL_TX $end
$var reg 1 ) CHNL_TX_ACK $end
$var reg 1 * CHNL_TX_CLK $end
$var reg 1 + CHNL_TX_DATA_REN $end
$var reg 1 , CHNL_TX_DATA_VALID $end
$var reg 1 - CHNL_TX_LAST $end
$var reg 1 . RST $end
$var reg 1 / \tState.00  $end
$var reg 1 0 \tState.01  $end
$var reg 1 1 \rState.00  $end
$var reg 1 2 \rState.01  $end
$var reg 1 3 TX_IN_PROGRESS $end
$var reg 1 4 CHNL_RX_DATA[127] $end
$var reg 1 5 CHNL_RX_DATA[126] $end
$var reg 1 6 CHNL_RX_DATA[125] $end
$var reg 1 7 CHNL_RX_DATA[124] $end
$var reg 1 8 CHNL_RX_DATA[123] $end
$var reg 1 9 CHNL_RX_DATA[122] $end
$var reg 1 : CHNL_RX_DATA[121] $end
$var reg 1 ; CHNL_RX_DATA[120] $end
$var reg 1 < CHNL_RX_DATA[119] $end
$var reg 1 = CHNL_RX_DATA[118] $end
$var reg 1 > CHNL_RX_DATA[117] $end
$var reg 1 ? CHNL_RX_DATA[116] $end
$var reg 1 @ CHNL_RX_DATA[115] $end
$var reg 1 A CHNL_RX_DATA[114] $end
$var reg 1 B CHNL_RX_DATA[113] $end
$var reg 1 C CHNL_RX_DATA[112] $end
$var reg 1 D CHNL_RX_DATA[111] $end
$var reg 1 E CHNL_RX_DATA[110] $end
$var reg 1 F CHNL_RX_DATA[109] $end
$var reg 1 G CHNL_RX_DATA[108] $end
$var reg 1 H CHNL_RX_DATA[107] $end
$var reg 1 I CHNL_RX_DATA[106] $end
$var reg 1 J CHNL_RX_DATA[105] $end
$var reg 1 K CHNL_RX_DATA[104] $end
$var reg 1 L CHNL_RX_DATA[103] $end
$var reg 1 M CHNL_RX_DATA[102] $end
$var reg 1 N CHNL_RX_DATA[101] $end
$var reg 1 O CHNL_RX_DATA[100] $end
$var reg 1 P CHNL_RX_DATA[99] $end
$var reg 1 Q CHNL_RX_DATA[98] $end
$var reg 1 R CHNL_RX_DATA[97] $end
$var reg 1 S CHNL_RX_DATA[96] $end
$var reg 1 T CHNL_RX_DATA[95] $end
$var reg 1 U CHNL_RX_DATA[94] $end
$var reg 1 V CHNL_RX_DATA[93] $end
$var reg 1 W CHNL_RX_DATA[92] $end
$var reg 1 X CHNL_RX_DATA[91] $end
$var reg 1 Y CHNL_RX_DATA[90] $end
$var reg 1 Z CHNL_RX_DATA[89] $end
$var reg 1 [ CHNL_RX_DATA[88] $end
$var reg 1 \ CHNL_RX_DATA[87] $end
$var reg 1 ] CHNL_RX_DATA[86] $end
$var reg 1 ^ CHNL_RX_DATA[85] $end
$var reg 1 _ CHNL_RX_DATA[84] $end
$var reg 1 ` CHNL_RX_DATA[83] $end
$var reg 1 a CHNL_RX_DATA[82] $end
$var reg 1 b CHNL_RX_DATA[81] $end
$var reg 1 c CHNL_RX_DATA[80] $end
$var reg 1 d CHNL_RX_DATA[79] $end
$var reg 1 e CHNL_RX_DATA[78] $end
$var reg 1 f CHNL_RX_DATA[77] $end
$var reg 1 g CHNL_RX_DATA[76] $end
$var reg 1 h CHNL_RX_DATA[75] $end
$var reg 1 i CHNL_RX_DATA[74] $end
$var reg 1 j CHNL_RX_DATA[73] $end
$var reg 1 k CHNL_RX_DATA[72] $end
$var reg 1 l CHNL_RX_DATA[71] $end
$var reg 1 m CHNL_RX_DATA[70] $end
$var reg 1 n CHNL_RX_DATA[69] $end
$var reg 1 o CHNL_RX_DATA[68] $end
$var reg 1 p CHNL_RX_DATA[67] $end
$var reg 1 q CHNL_RX_DATA[66] $end
$var reg 1 r CHNL_RX_DATA[65] $end
$var reg 1 s CHNL_RX_DATA[64] $end
$var reg 1 t CHNL_RX_DATA[63] $end
$var reg 1 u CHNL_RX_DATA[62] $end
$var reg 1 v CHNL_RX_DATA[61] $end
$var reg 1 w CHNL_RX_DATA[60] $end
$var reg 1 x CHNL_RX_DATA[59] $end
$var reg 1 y CHNL_RX_DATA[58] $end
$var reg 1 z CHNL_RX_DATA[57] $end
$var reg 1 { CHNL_RX_DATA[56] $end
$var reg 1 | CHNL_RX_DATA[55] $end
$var reg 1 } CHNL_RX_DATA[54] $end
$var reg 1 ~ CHNL_RX_DATA[53] $end
$var reg 1 !! CHNL_RX_DATA[52] $end
$var reg 1 !" CHNL_RX_DATA[51] $end
$var reg 1 !# CHNL_RX_DATA[50] $end
$var reg 1 !$ CHNL_RX_DATA[49] $end
$var reg 1 !% CHNL_RX_DATA[48] $end
$var reg 1 !& CHNL_RX_DATA[47] $end
$var reg 1 !' CHNL_RX_DATA[46] $end
$var reg 1 !( CHNL_RX_DATA[45] $end
$var reg 1 !) CHNL_RX_DATA[44] $end
$var reg 1 !* CHNL_RX_DATA[43] $end
$var reg 1 !+ CHNL_RX_DATA[42] $end
$var reg 1 !, CHNL_RX_DATA[41] $end
$var reg 1 !- CHNL_RX_DATA[40] $end
$var reg 1 !. CHNL_RX_DATA[39] $end
$var reg 1 !/ CHNL_RX_DATA[38] $end
$var reg 1 !0 CHNL_RX_DATA[37] $end
$var reg 1 !1 CHNL_RX_DATA[36] $end
$var reg 1 !2 CHNL_RX_DATA[35] $end
$var reg 1 !3 CHNL_RX_DATA[34] $end
$var reg 1 !4 CHNL_RX_DATA[33] $end
$var reg 1 !5 CHNL_RX_DATA[32] $end
$var reg 1 !6 CHNL_RX_DATA[31] $end
$var reg 1 !7 CHNL_RX_DATA[30] $end
$var reg 1 !8 CHNL_RX_DATA[29] $end
$var reg 1 !9 CHNL_RX_DATA[28] $end
$var reg 1 !: CHNL_RX_DATA[27] $end
$var reg 1 !; CHNL_RX_DATA[26] $end
$var reg 1 !< CHNL_RX_DATA[25] $end
$var reg 1 != CHNL_RX_DATA[24] $end
$var reg 1 !> CHNL_RX_DATA[23] $end
$var reg 1 !? CHNL_RX_DATA[22] $end
$var reg 1 !@ CHNL_RX_DATA[21] $end
$var reg 1 !A CHNL_RX_DATA[20] $end
$var reg 1 !B CHNL_RX_DATA[19] $end
$var reg 1 !C CHNL_RX_DATA[18] $end
$var reg 1 !D CHNL_RX_DATA[17] $end
$var reg 1 !E CHNL_RX_DATA[16] $end
$var reg 1 !F CHNL_RX_DATA[15] $end
$var reg 1 !G CHNL_RX_DATA[14] $end
$var reg 1 !H CHNL_RX_DATA[13] $end
$var reg 1 !I CHNL_RX_DATA[12] $end
$var reg 1 !J CHNL_RX_DATA[11] $end
$var reg 1 !K CHNL_RX_DATA[10] $end
$var reg 1 !L CHNL_RX_DATA[9] $end
$var reg 1 !M CHNL_RX_DATA[8] $end
$var reg 1 !N CHNL_RX_DATA[7] $end
$var reg 1 !O CHNL_RX_DATA[6] $end
$var reg 1 !P CHNL_RX_DATA[5] $end
$var reg 1 !Q CHNL_RX_DATA[4] $end
$var reg 1 !R CHNL_RX_DATA[3] $end
$var reg 1 !S CHNL_RX_DATA[2] $end
$var reg 1 !T CHNL_RX_DATA[1] $end
$var reg 1 !U CHNL_RX_DATA[0] $end
$var reg 1 !V CHNL_RX_OFF[30] $end
$var reg 1 !W CHNL_RX_OFF[29] $end
$var reg 1 !X CHNL_RX_OFF[28] $end
$var reg 1 !Y CHNL_RX_OFF[27] $end
$var reg 1 !Z CHNL_RX_OFF[26] $end
$var reg 1 ![ CHNL_RX_OFF[25] $end
$var reg 1 !\ CHNL_RX_OFF[24] $end
$var reg 1 !] CHNL_RX_OFF[23] $end
$var reg 1 !^ CHNL_RX_OFF[22] $end
$var reg 1 !_ CHNL_RX_OFF[21] $end
$var reg 1 !` CHNL_RX_OFF[20] $end
$var reg 1 !a CHNL_RX_OFF[19] $end
$var reg 1 !b CHNL_RX_OFF[18] $end
$var reg 1 !c CHNL_RX_OFF[17] $end
$var reg 1 !d CHNL_RX_OFF[16] $end
$var reg 1 !e CHNL_RX_OFF[15] $end
$var reg 1 !f CHNL_RX_OFF[14] $end
$var reg 1 !g CHNL_RX_OFF[13] $end
$var reg 1 !h CHNL_RX_OFF[12] $end
$var reg 1 !i CHNL_RX_OFF[11] $end
$var reg 1 !j CHNL_RX_OFF[10] $end
$var reg 1 !k CHNL_RX_OFF[9] $end
$var reg 1 !l CHNL_RX_OFF[8] $end
$var reg 1 !m CHNL_RX_OFF[7] $end
$var reg 1 !n CHNL_RX_OFF[6] $end
$var reg 1 !o CHNL_RX_OFF[5] $end
$var reg 1 !p CHNL_RX_OFF[4] $end
$var reg 1 !q CHNL_RX_OFF[3] $end
$var reg 1 !r CHNL_RX_OFF[2] $end
$var reg 1 !s CHNL_RX_OFF[1] $end
$var reg 1 !t CHNL_RX_OFF[0] $end
$var reg 1 !u CHNL_TX_DATA[127] $end
$var reg 1 !v CHNL_TX_DATA[126] $end
$var reg 1 !w CHNL_TX_DATA[125] $end
$var reg 1 !x CHNL_TX_DATA[124] $end
$var reg 1 !y CHNL_TX_DATA[123] $end
$var reg 1 !z CHNL_TX_DATA[122] $end
$var reg 1 !{ CHNL_TX_DATA[121] $end
$var reg 1 !| CHNL_TX_DATA[120] $end
$var reg 1 !} CHNL_TX_DATA[119] $end
$var reg 1 !~ CHNL_TX_DATA[118] $end
$var reg 1 "! CHNL_TX_DATA[117] $end
$var reg 1 "" CHNL_TX_DATA[116] $end
$var reg 1 "# CHNL_TX_DATA[115] $end
$var reg 1 "$ CHNL_TX_DATA[114] $end
$var reg 1 "% CHNL_TX_DATA[113] $end
$var reg 1 "& CHNL_TX_DATA[112] $end
$var reg 1 "' CHNL_TX_DATA[111] $end
$var reg 1 "( CHNL_TX_DATA[110] $end
$var reg 1 ") CHNL_TX_DATA[109] $end
$var reg 1 "* CHNL_TX_DATA[108] $end
$var reg 1 "+ CHNL_TX_DATA[107] $end
$var reg 1 ", CHNL_TX_DATA[106] $end
$var reg 1 "- CHNL_TX_DATA[105] $end
$var reg 1 ". CHNL_TX_DATA[104] $end
$var reg 1 "/ CHNL_TX_DATA[103] $end
$var reg 1 "0 CHNL_TX_DATA[102] $end
$var reg 1 "1 CHNL_TX_DATA[101] $end
$var reg 1 "2 CHNL_TX_DATA[100] $end
$var reg 1 "3 CHNL_TX_DATA[99] $end
$var reg 1 "4 CHNL_TX_DATA[98] $end
$var reg 1 "5 CHNL_TX_DATA[97] $end
$var reg 1 "6 CHNL_TX_DATA[96] $end
$var reg 1 "7 CHNL_TX_DATA[95] $end
$var reg 1 "8 CHNL_TX_DATA[94] $end
$var reg 1 "9 CHNL_TX_DATA[93] $end
$var reg 1 ": CHNL_TX_DATA[92] $end
$var reg 1 "; CHNL_TX_DATA[91] $end
$var reg 1 "< CHNL_TX_DATA[90] $end
$var reg 1 "= CHNL_TX_DATA[89] $end
$var reg 1 "> CHNL_TX_DATA[88] $end
$var reg 1 "? CHNL_TX_DATA[87] $end
$var reg 1 "@ CHNL_TX_DATA[86] $end
$var reg 1 "A CHNL_TX_DATA[85] $end
$var reg 1 "B CHNL_TX_DATA[84] $end
$var reg 1 "C CHNL_TX_DATA[83] $end
$var reg 1 "D CHNL_TX_DATA[82] $end
$var reg 1 "E CHNL_TX_DATA[81] $end
$var reg 1 "F CHNL_TX_DATA[80] $end
$var reg 1 "G CHNL_TX_DATA[79] $end
$var reg 1 "H CHNL_TX_DATA[78] $end
$var reg 1 "I CHNL_TX_DATA[77] $end
$var reg 1 "J CHNL_TX_DATA[76] $end
$var reg 1 "K CHNL_TX_DATA[75] $end
$var reg 1 "L CHNL_TX_DATA[74] $end
$var reg 1 "M CHNL_TX_DATA[73] $end
$var reg 1 "N CHNL_TX_DATA[72] $end
$var reg 1 "O CHNL_TX_DATA[71] $end
$var reg 1 "P CHNL_TX_DATA[70] $end
$var reg 1 "Q CHNL_TX_DATA[69] $end
$var reg 1 "R CHNL_TX_DATA[68] $end
$var reg 1 "S CHNL_TX_DATA[67] $end
$var reg 1 "T CHNL_TX_DATA[66] $end
$var reg 1 "U CHNL_TX_DATA[65] $end
$var reg 1 "V CHNL_TX_DATA[64] $end
$var reg 1 "W CHNL_TX_DATA[63] $end
$var reg 1 "X CHNL_TX_DATA[62] $end
$var reg 1 "Y CHNL_TX_DATA[61] $end
$var reg 1 "Z CHNL_TX_DATA[60] $end
$var reg 1 "[ CHNL_TX_DATA[59] $end
$var reg 1 "\ CHNL_TX_DATA[58] $end
$var reg 1 "] CHNL_TX_DATA[57] $end
$var reg 1 "^ CHNL_TX_DATA[56] $end
$var reg 1 "_ CHNL_TX_DATA[55] $end
$var reg 1 "` CHNL_TX_DATA[54] $end
$var reg 1 "a CHNL_TX_DATA[53] $end
$var reg 1 "b CHNL_TX_DATA[52] $end
$var reg 1 "c CHNL_TX_DATA[51] $end
$var reg 1 "d CHNL_TX_DATA[50] $end
$var reg 1 "e CHNL_TX_DATA[49] $end
$var reg 1 "f CHNL_TX_DATA[48] $end
$var reg 1 "g CHNL_TX_DATA[47] $end
$var reg 1 "h CHNL_TX_DATA[46] $end
$var reg 1 "i CHNL_TX_DATA[45] $end
$var reg 1 "j CHNL_TX_DATA[44] $end
$var reg 1 "k CHNL_TX_DATA[43] $end
$var reg 1 "l CHNL_TX_DATA[42] $end
$var reg 1 "m CHNL_TX_DATA[41] $end
$var reg 1 "n CHNL_TX_DATA[40] $end
$var reg 1 "o CHNL_TX_DATA[39] $end
$var reg 1 "p CHNL_TX_DATA[38] $end
$var reg 1 "q CHNL_TX_DATA[37] $end
$var reg 1 "r CHNL_TX_DATA[36] $end
$var reg 1 "s CHNL_TX_DATA[35] $end
$var reg 1 "t CHNL_TX_DATA[34] $end
$var reg 1 "u CHNL_TX_DATA[33] $end
$var reg 1 "v CHNL_TX_DATA[32] $end
$var reg 1 "w CHNL_TX_DATA[31] $end
$var reg 1 "x CHNL_TX_DATA[30] $end
$var reg 1 "y CHNL_TX_DATA[29] $end
$var reg 1 "z CHNL_TX_DATA[28] $end
$var reg 1 "{ CHNL_TX_DATA[27] $end
$var reg 1 "| CHNL_TX_DATA[26] $end
$var reg 1 "} CHNL_TX_DATA[25] $end
$var reg 1 "~ CHNL_TX_DATA[24] $end
$var reg 1 #! CHNL_TX_DATA[23] $end
$var reg 1 #" CHNL_TX_DATA[22] $end
$var reg 1 ## CHNL_TX_DATA[21] $end
$var reg 1 #$ CHNL_TX_DATA[20] $end
$var reg 1 #% CHNL_TX_DATA[19] $end
$var reg 1 #& CHNL_TX_DATA[18] $end
$var reg 1 #' CHNL_TX_DATA[17] $end
$var reg 1 #( CHNL_TX_DATA[16] $end
$var reg 1 #) CHNL_TX_DATA[15] $end
$var reg 1 #* CHNL_TX_DATA[14] $end
$var reg 1 #+ CHNL_TX_DATA[13] $end
$var reg 1 #, CHNL_TX_DATA[12] $end
$var reg 1 #- CHNL_TX_DATA[11] $end
$var reg 1 #. CHNL_TX_DATA[10] $end
$var reg 1 #/ CHNL_TX_DATA[9] $end
$var reg 1 #0 CHNL_TX_DATA[8] $end
$var reg 1 #1 CHNL_TX_DATA[7] $end
$var reg 1 #2 CHNL_TX_DATA[6] $end
$var reg 1 #3 CHNL_TX_DATA[5] $end
$var reg 1 #4 CHNL_TX_DATA[4] $end
$var reg 1 #5 CHNL_TX_DATA[3] $end
$var reg 1 #6 CHNL_TX_DATA[2] $end
$var reg 1 #7 CHNL_TX_DATA[1] $end
$var reg 1 #8 CHNL_TX_DATA[0] $end
$var reg 1 #9 CHNL_TX_LEN[31] $end
$var reg 1 #: CHNL_TX_LEN[30] $end
$var reg 1 #; CHNL_TX_LEN[29] $end
$var reg 1 #< CHNL_TX_LEN[28] $end
$var reg 1 #= CHNL_TX_LEN[27] $end
$var reg 1 #> CHNL_TX_LEN[26] $end
$var reg 1 #? CHNL_TX_LEN[25] $end
$var reg 1 #@ CHNL_TX_LEN[24] $end
$var reg 1 #A CHNL_TX_LEN[23] $end
$var reg 1 #B CHNL_TX_LEN[22] $end
$var reg 1 #C CHNL_TX_LEN[21] $end
$var reg 1 #D CHNL_TX_LEN[20] $end
$var reg 1 #E CHNL_TX_LEN[19] $end
$var reg 1 #F CHNL_TX_LEN[18] $end
$var reg 1 #G CHNL_TX_LEN[17] $end
$var reg 1 #H CHNL_TX_LEN[16] $end
$var reg 1 #I CHNL_TX_LEN[15] $end
$var reg 1 #J CHNL_TX_LEN[14] $end
$var reg 1 #K CHNL_TX_LEN[13] $end
$var reg 1 #L CHNL_TX_LEN[12] $end
$var reg 1 #M CHNL_TX_LEN[11] $end
$var reg 1 #N CHNL_TX_LEN[10] $end
$var reg 1 #O CHNL_TX_LEN[9] $end
$var reg 1 #P CHNL_TX_LEN[8] $end
$var reg 1 #Q CHNL_TX_LEN[7] $end
$var reg 1 #R CHNL_TX_LEN[6] $end
$var reg 1 #S CHNL_TX_LEN[5] $end
$var reg 1 #T CHNL_TX_LEN[4] $end
$var reg 1 #U CHNL_TX_LEN[3] $end
$var reg 1 #V CHNL_TX_LEN[2] $end
$var reg 1 #W CHNL_TX_LEN[1] $end
$var reg 1 #X CHNL_TX_LEN[0] $end
$var reg 1 #Y CHNL_TX_OFF[30] $end
$var reg 1 #Z CHNL_TX_OFF[29] $end
$var reg 1 #[ CHNL_TX_OFF[28] $end
$var reg 1 #\ CHNL_TX_OFF[27] $end
$var reg 1 #] CHNL_TX_OFF[26] $end
$var reg 1 #^ CHNL_TX_OFF[25] $end
$var reg 1 #_ CHNL_TX_OFF[24] $end
$var reg 1 #` CHNL_TX_OFF[23] $end
$var reg 1 #a CHNL_TX_OFF[22] $end
$var reg 1 #b CHNL_TX_OFF[21] $end
$var reg 1 #c CHNL_TX_OFF[20] $end
$var reg 1 #d CHNL_TX_OFF[19] $end
$var reg 1 #e CHNL_TX_OFF[18] $end
$var reg 1 #f CHNL_TX_OFF[17] $end
$var reg 1 #g CHNL_TX_OFF[16] $end
$var reg 1 #h CHNL_TX_OFF[15] $end
$var reg 1 #i CHNL_TX_OFF[14] $end
$var reg 1 #j CHNL_TX_OFF[13] $end
$var reg 1 #k CHNL_TX_OFF[12] $end
$var reg 1 #l CHNL_TX_OFF[11] $end
$var reg 1 #m CHNL_TX_OFF[10] $end
$var reg 1 #n CHNL_TX_OFF[9] $end
$var reg 1 #o CHNL_TX_OFF[8] $end
$var reg 1 #p CHNL_TX_OFF[7] $end
$var reg 1 #q CHNL_TX_OFF[6] $end
$var reg 1 #r CHNL_TX_OFF[5] $end
$var reg 1 #s CHNL_TX_OFF[4] $end
$var reg 1 #t CHNL_TX_OFF[3] $end
$var reg 1 #u CHNL_TX_OFF[2] $end
$var reg 1 #v CHNL_TX_OFF[1] $end
$var reg 1 #w CHNL_TX_OFF[0] $end
$var reg 1 #x rCount[31] $end
$var reg 1 #y rCount[30] $end
$var reg 1 #z rCount[29] $end
$var reg 1 #{ rCount[28] $end
$var reg 1 #| rCount[27] $end
$var reg 1 #} rCount[26] $end
$var reg 1 #~ rCount[25] $end
$var reg 1 $! rCount[24] $end
$var reg 1 $" rCount[23] $end
$var reg 1 $# rCount[22] $end
$var reg 1 $$ rCount[21] $end
$var reg 1 $% rCount[20] $end
$var reg 1 $& rCount[19] $end
$var reg 1 $' rCount[18] $end
$var reg 1 $( rCount[17] $end
$var reg 1 $) rCount[16] $end
$var reg 1 $* rCount[15] $end
$var reg 1 $+ rCount[14] $end
$var reg 1 $, rCount[13] $end
$var reg 1 $- rCount[12] $end
$var reg 1 $. rCount[11] $end
$var reg 1 $/ rCount[10] $end
$var reg 1 $0 rCount[9] $end
$var reg 1 $1 rCount[8] $end
$var reg 1 $2 rCount[7] $end
$var reg 1 $3 rCount[6] $end
$var reg 1 $4 rCount[5] $end
$var reg 1 $5 rCount[4] $end
$var reg 1 $6 rCount[3] $end
$var reg 1 $7 rCount[2] $end
$var reg 1 $8 rCount[1] $end
$var reg 1 $9 rCount[0] $end
$var reg 1 $: rData[127] $end
$var reg 1 $; rData[126] $end
$var reg 1 $< rData[125] $end
$var reg 1 $= rData[124] $end
$var reg 1 $> rData[123] $end
$var reg 1 $? rData[122] $end
$var reg 1 $@ rData[121] $end
$var reg 1 $A rData[120] $end
$var reg 1 $B rData[119] $end
$var reg 1 $C rData[118] $end
$var reg 1 $D rData[117] $end
$var reg 1 $E rData[116] $end
$var reg 1 $F rData[115] $end
$var reg 1 $G rData[114] $end
$var reg 1 $H rData[113] $end
$var reg 1 $I rData[112] $end
$var reg 1 $J rData[111] $end
$var reg 1 $K rData[110] $end
$var reg 1 $L rData[109] $end
$var reg 1 $M rData[108] $end
$var reg 1 $N rData[107] $end
$var reg 1 $O rData[106] $end
$var reg 1 $P rData[105] $end
$var reg 1 $Q rData[104] $end
$var reg 1 $R rData[103] $end
$var reg 1 $S rData[102] $end
$var reg 1 $T rData[101] $end
$var reg 1 $U rData[100] $end
$var reg 1 $V rData[99] $end
$var reg 1 $W rData[98] $end
$var reg 1 $X rData[97] $end
$var reg 1 $Y rData[96] $end
$var reg 1 $Z rData[95] $end
$var reg 1 $[ rData[94] $end
$var reg 1 $\ rData[93] $end
$var reg 1 $] rData[92] $end
$var reg 1 $^ rData[91] $end
$var reg 1 $_ rData[90] $end
$var reg 1 $` rData[89] $end
$var reg 1 $a rData[88] $end
$var reg 1 $b rData[87] $end
$var reg 1 $c rData[86] $end
$var reg 1 $d rData[85] $end
$var reg 1 $e rData[84] $end
$var reg 1 $f rData[83] $end
$var reg 1 $g rData[82] $end
$var reg 1 $h rData[81] $end
$var reg 1 $i rData[80] $end
$var reg 1 $j rData[79] $end
$var reg 1 $k rData[78] $end
$var reg 1 $l rData[77] $end
$var reg 1 $m rData[76] $end
$var reg 1 $n rData[75] $end
$var reg 1 $o rData[74] $end
$var reg 1 $p rData[73] $end
$var reg 1 $q rData[72] $end
$var reg 1 $r rData[71] $end
$var reg 1 $s rData[70] $end
$var reg 1 $t rData[69] $end
$var reg 1 $u rData[68] $end
$var reg 1 $v rData[67] $end
$var reg 1 $w rData[66] $end
$var reg 1 $x rData[65] $end
$var reg 1 $y rData[64] $end
$var reg 1 $z rData[63] $end
$var reg 1 ${ rData[62] $end
$var reg 1 $| rData[61] $end
$var reg 1 $} rData[60] $end
$var reg 1 $~ rData[59] $end
$var reg 1 %! rData[58] $end
$var reg 1 %" rData[57] $end
$var reg 1 %# rData[56] $end
$var reg 1 %$ rData[55] $end
$var reg 1 %% rData[54] $end
$var reg 1 %& rData[53] $end
$var reg 1 %' rData[52] $end
$var reg 1 %( rData[51] $end
$var reg 1 %) rData[50] $end
$var reg 1 %* rData[49] $end
$var reg 1 %+ rData[48] $end
$var reg 1 %, rData[47] $end
$var reg 1 %- rData[46] $end
$var reg 1 %. rData[45] $end
$var reg 1 %/ rData[44] $end
$var reg 1 %0 rData[43] $end
$var reg 1 %1 rData[42] $end
$var reg 1 %2 rData[41] $end
$var reg 1 %3 rData[40] $end
$var reg 1 %4 rData[39] $end
$var reg 1 %5 rData[38] $end
$var reg 1 %6 rData[37] $end
$var reg 1 %7 rData[36] $end
$var reg 1 %8 rData[35] $end
$var reg 1 %9 rData[34] $end
$var reg 1 %: rData[33] $end
$var reg 1 %; rData[32] $end
$var reg 1 %< rData[31] $end
$var reg 1 %= rData[30] $end
$var reg 1 %> rData[29] $end
$var reg 1 %? rData[28] $end
$var reg 1 %@ rData[27] $end
$var reg 1 %A rData[26] $end
$var reg 1 %B rData[25] $end
$var reg 1 %C rData[24] $end
$var reg 1 %D rData[23] $end
$var reg 1 %E rData[22] $end
$var reg 1 %F rData[21] $end
$var reg 1 %G rData[20] $end
$var reg 1 %H rData[19] $end
$var reg 1 %I rData[18] $end
$var reg 1 %J rData[17] $end
$var reg 1 %K rData[16] $end
$var reg 1 %L rData[15] $end
$var reg 1 %M rData[14] $end
$var reg 1 %N rData[13] $end
$var reg 1 %O rData[12] $end
$var reg 1 %P rData[11] $end
$var reg 1 %Q rData[10] $end
$var reg 1 %R rData[9] $end
$var reg 1 %S rData[8] $end
$var reg 1 %T rData[7] $end
$var reg 1 %U rData[6] $end
$var reg 1 %V rData[5] $end
$var reg 1 %W rData[4] $end
$var reg 1 %X rData[3] $end
$var reg 1 %Y rData[2] $end
$var reg 1 %Z rData[1] $end
$var reg 1 %[ rData[0] $end
$var reg 1 %\ tCount[31] $end
$var reg 1 %] tCount[30] $end
$var reg 1 %^ tCount[29] $end
$var reg 1 %_ tCount[28] $end
$var reg 1 %` tCount[27] $end
$var reg 1 %a tCount[26] $end
$var reg 1 %b tCount[25] $end
$var reg 1 %c tCount[24] $end
$var reg 1 %d tCount[23] $end
$var reg 1 %e tCount[22] $end
$var reg 1 %f tCount[21] $end
$var reg 1 %g tCount[20] $end
$var reg 1 %h tCount[19] $end
$var reg 1 %i tCount[18] $end
$var reg 1 %j tCount[17] $end
$var reg 1 %k tCount[16] $end
$var reg 1 %l tCount[15] $end
$var reg 1 %m tCount[14] $end
$var reg 1 %n tCount[13] $end
$var reg 1 %o tCount[12] $end
$var reg 1 %p tCount[11] $end
$var reg 1 %q tCount[10] $end
$var reg 1 %r tCount[9] $end
$var reg 1 %s tCount[8] $end
$var reg 1 %t tCount[7] $end
$var reg 1 %u tCount[6] $end
$var reg 1 %v tCount[5] $end
$var reg 1 %w tCount[4] $end
$var reg 1 %x tCount[3] $end
$var reg 1 %y tCount[2] $end
$var reg 1 %z tCount[1] $end
$var reg 1 %{ tCount[0] $end
$upscope $end
$scope module riffa $end
$scope module engine_layer_inst $end
$scope module rx_engine_classic_inst $end
$scope module rxr_engine_inst $end
$var reg 1 %| RST_BUS $end
$var reg 1 %} RST_LOGIC $end
$var reg 1 %~ DONE_RXR_RST $end
$var reg 1 &! RX_TLP[127] $end
$var reg 1 &" RX_TLP[126] $end
$var reg 1 &# RX_TLP[125] $end
$var reg 1 &$ RX_TLP[124] $end
$var reg 1 &% RX_TLP[123] $end
$var reg 1 && RX_TLP[122] $end
$var reg 1 &' RX_TLP[121] $end
$var reg 1 &( RX_TLP[120] $end
$var reg 1 &) RX_TLP[119] $end
$var reg 1 &* RX_TLP[118] $end
$var reg 1 &+ RX_TLP[117] $end
$var reg 1 &, RX_TLP[116] $end
$var reg 1 &- RX_TLP[115] $end
$var reg 1 &. RX_TLP[114] $end
$var reg 1 &/ RX_TLP[113] $end
$var reg 1 &0 RX_TLP[112] $end
$var reg 1 &1 RX_TLP[111] $end
$var reg 1 &2 RX_TLP[110] $end
$var reg 1 &3 RX_TLP[109] $end
$var reg 1 &4 RX_TLP[108] $end
$var reg 1 &5 RX_TLP[107] $end
$var reg 1 &6 RX_TLP[106] $end
$var reg 1 &7 RX_TLP[105] $end
$var reg 1 &8 RX_TLP[104] $end
$var reg 1 &9 RX_TLP[103] $end
$var reg 1 &: RX_TLP[102] $end
$var reg 1 &; RX_TLP[101] $end
$var reg 1 &< RX_TLP[100] $end
$var reg 1 &= RX_TLP[99] $end
$var reg 1 &> RX_TLP[98] $end
$var reg 1 &? RX_TLP[97] $end
$var reg 1 &@ RX_TLP[96] $end
$var reg 1 &A RX_TLP[95] $end
$var reg 1 &B RX_TLP[94] $end
$var reg 1 &C RX_TLP[93] $end
$var reg 1 &D RX_TLP[92] $end
$var reg 1 &E RX_TLP[91] $end
$var reg 1 &F RX_TLP[90] $end
$var reg 1 &G RX_TLP[89] $end
$var reg 1 &H RX_TLP[88] $end
$var reg 1 &I RX_TLP[87] $end
$var reg 1 &J RX_TLP[86] $end
$var reg 1 &K RX_TLP[85] $end
$var reg 1 &L RX_TLP[84] $end
$var reg 1 &M RX_TLP[83] $end
$var reg 1 &N RX_TLP[82] $end
$var reg 1 &O RX_TLP[81] $end
$var reg 1 &P RX_TLP[80] $end
$var reg 1 &Q RX_TLP[79] $end
$var reg 1 &R RX_TLP[78] $end
$var reg 1 &S RX_TLP[77] $end
$var reg 1 &T RX_TLP[76] $end
$var reg 1 &U RX_TLP[75] $end
$var reg 1 &V RX_TLP[74] $end
$var reg 1 &W RX_TLP[73] $end
$var reg 1 &X RX_TLP[72] $end
$var reg 1 &Y RX_TLP[71] $end
$var reg 1 &Z RX_TLP[70] $end
$var reg 1 &[ RX_TLP[69] $end
$var reg 1 &\ RX_TLP[68] $end
$var reg 1 &] RX_TLP[67] $end
$var reg 1 &^ RX_TLP[66] $end
$var reg 1 &_ RX_TLP[65] $end
$var reg 1 &` RX_TLP[64] $end
$var reg 1 &a RX_TLP[63] $end
$var reg 1 &b RX_TLP[62] $end
$var reg 1 &c RX_TLP[61] $end
$var reg 1 &d RX_TLP[60] $end
$var reg 1 &e RX_TLP[59] $end
$var reg 1 &f RX_TLP[58] $end
$var reg 1 &g RX_TLP[57] $end
$var reg 1 &h RX_TLP[56] $end
$var reg 1 &i RX_TLP[55] $end
$var reg 1 &j RX_TLP[54] $end
$var reg 1 &k RX_TLP[53] $end
$var reg 1 &l RX_TLP[52] $end
$var reg 1 &m RX_TLP[51] $end
$var reg 1 &n RX_TLP[50] $end
$var reg 1 &o RX_TLP[49] $end
$var reg 1 &p RX_TLP[48] $end
$var reg 1 &q RX_TLP[47] $end
$var reg 1 &r RX_TLP[46] $end
$var reg 1 &s RX_TLP[45] $end
$var reg 1 &t RX_TLP[44] $end
$var reg 1 &u RX_TLP[43] $end
$var reg 1 &v RX_TLP[42] $end
$var reg 1 &w RX_TLP[41] $end
$var reg 1 &x RX_TLP[40] $end
$var reg 1 &y RX_TLP[39] $end
$var reg 1 &z RX_TLP[38] $end
$var reg 1 &{ RX_TLP[37] $end
$var reg 1 &| RX_TLP[36] $end
$var reg 1 &} RX_TLP[35] $end
$var reg 1 &~ RX_TLP[34] $end
$var reg 1 '! RX_TLP[33] $end
$var reg 1 '" RX_TLP[32] $end
$var reg 1 '# RX_TLP[31] $end
$var reg 1 '$ RX_TLP[30] $end
$var reg 1 '% RX_TLP[29] $end
$var reg 1 '& RX_TLP[28] $end
$var reg 1 '' RX_TLP[27] $end
$var reg 1 '( RX_TLP[26] $end
$var reg 1 ') RX_TLP[25] $end
$var reg 1 '* RX_TLP[24] $end
$var reg 1 '+ RX_TLP[23] $end
$var reg 1 ', RX_TLP[22] $end
$var reg 1 '- RX_TLP[21] $end
$var reg 1 '. RX_TLP[20] $end
$var reg 1 '/ RX_TLP[19] $end
$var reg 1 '0 RX_TLP[18] $end
$var reg 1 '1 RX_TLP[17] $end
$var reg 1 '2 RX_TLP[16] $end
$var reg 1 '3 RX_TLP[15] $end
$var reg 1 '4 RX_TLP[14] $end
$var reg 1 '5 RX_TLP[13] $end
$var reg 1 '6 RX_TLP[12] $end
$var reg 1 '7 RX_TLP[11] $end
$var reg 1 '8 RX_TLP[10] $end
$var reg 1 '9 RX_TLP[9] $end
$var reg 1 ': RX_TLP[8] $end
$var reg 1 '; RX_TLP[7] $end
$var reg 1 '< RX_TLP[6] $end
$var reg 1 '= RX_TLP[5] $end
$var reg 1 '> RX_TLP[4] $end
$var reg 1 '? RX_TLP[3] $end
$var reg 1 '@ RX_TLP[2] $end
$var reg 1 'A RX_TLP[1] $end
$var reg 1 'B RX_TLP[0] $end
$var reg 1 'C RX_TLP_VALID $end
$var reg 1 'D RX_TLP_START_FLAG $end
$var reg 1 'E RX_TLP_START_OFFSET[3] $end
$var reg 1 'F RX_TLP_START_OFFSET[2] $end
$var reg 1 'G RX_TLP_START_OFFSET[1] $end
$var reg 1 'H RX_TLP_START_OFFSET[0] $end
$var reg 1 'I RX_TLP_END_FLAG $end
$var reg 1 'J RX_TLP_END_OFFSET[3] $end
$var reg 1 'K RX_TLP_END_OFFSET[2] $end
$var reg 1 'L RX_TLP_END_OFFSET[1] $end
$var reg 1 'M RX_TLP_END_OFFSET[0] $end
$var reg 1 'N RX_TLP_BAR_DECODE[7] $end
$var reg 1 'O RX_TLP_BAR_DECODE[6] $end
$var reg 1 'P RX_TLP_BAR_DECODE[5] $end
$var reg 1 'Q RX_TLP_BAR_DECODE[4] $end
$var reg 1 'R RX_TLP_BAR_DECODE[3] $end
$var reg 1 'S RX_TLP_BAR_DECODE[2] $end
$var reg 1 'T RX_TLP_BAR_DECODE[1] $end
$var reg 1 'U RX_TLP_BAR_DECODE[0] $end
$var reg 1 'V RXR_DATA[127] $end
$var reg 1 'W RXR_DATA[126] $end
$var reg 1 'X RXR_DATA[125] $end
$var reg 1 'Y RXR_DATA[124] $end
$var reg 1 'Z RXR_DATA[123] $end
$var reg 1 '[ RXR_DATA[122] $end
$var reg 1 '\ RXR_DATA[121] $end
$var reg 1 '] RXR_DATA[120] $end
$var reg 1 '^ RXR_DATA[119] $end
$var reg 1 '_ RXR_DATA[118] $end
$var reg 1 '` RXR_DATA[117] $end
$var reg 1 'a RXR_DATA[116] $end
$var reg 1 'b RXR_DATA[115] $end
$var reg 1 'c RXR_DATA[114] $end
$var reg 1 'd RXR_DATA[113] $end
$var reg 1 'e RXR_DATA[112] $end
$var reg 1 'f RXR_DATA[111] $end
$var reg 1 'g RXR_DATA[110] $end
$var reg 1 'h RXR_DATA[109] $end
$var reg 1 'i RXR_DATA[108] $end
$var reg 1 'j RXR_DATA[107] $end
$var reg 1 'k RXR_DATA[106] $end
$var reg 1 'l RXR_DATA[105] $end
$var reg 1 'm RXR_DATA[104] $end
$var reg 1 'n RXR_DATA[103] $end
$var reg 1 'o RXR_DATA[102] $end
$var reg 1 'p RXR_DATA[101] $end
$var reg 1 'q RXR_DATA[100] $end
$var reg 1 'r RXR_DATA[99] $end
$var reg 1 's RXR_DATA[98] $end
$var reg 1 't RXR_DATA[97] $end
$var reg 1 'u RXR_DATA[96] $end
$var reg 1 'v RXR_DATA[95] $end
$var reg 1 'w RXR_DATA[94] $end
$var reg 1 'x RXR_DATA[93] $end
$var reg 1 'y RXR_DATA[92] $end
$var reg 1 'z RXR_DATA[91] $end
$var reg 1 '{ RXR_DATA[90] $end
$var reg 1 '| RXR_DATA[89] $end
$var reg 1 '} RXR_DATA[88] $end
$var reg 1 '~ RXR_DATA[87] $end
$var reg 1 (! RXR_DATA[86] $end
$var reg 1 (" RXR_DATA[85] $end
$var reg 1 (# RXR_DATA[84] $end
$var reg 1 ($ RXR_DATA[83] $end
$var reg 1 (% RXR_DATA[82] $end
$var reg 1 (& RXR_DATA[81] $end
$var reg 1 (' RXR_DATA[80] $end
$var reg 1 (( RXR_DATA[79] $end
$var reg 1 () RXR_DATA[78] $end
$var reg 1 (* RXR_DATA[77] $end
$var reg 1 (+ RXR_DATA[76] $end
$var reg 1 (, RXR_DATA[75] $end
$var reg 1 (- RXR_DATA[74] $end
$var reg 1 (. RXR_DATA[73] $end
$var reg 1 (/ RXR_DATA[72] $end
$var reg 1 (0 RXR_DATA[71] $end
$var reg 1 (1 RXR_DATA[70] $end
$var reg 1 (2 RXR_DATA[69] $end
$var reg 1 (3 RXR_DATA[68] $end
$var reg 1 (4 RXR_DATA[67] $end
$var reg 1 (5 RXR_DATA[66] $end
$var reg 1 (6 RXR_DATA[65] $end
$var reg 1 (7 RXR_DATA[64] $end
$var reg 1 (8 RXR_DATA[63] $end
$var reg 1 (9 RXR_DATA[62] $end
$var reg 1 (: RXR_DATA[61] $end
$var reg 1 (; RXR_DATA[60] $end
$var reg 1 (< RXR_DATA[59] $end
$var reg 1 (= RXR_DATA[58] $end
$var reg 1 (> RXR_DATA[57] $end
$var reg 1 (? RXR_DATA[56] $end
$var reg 1 (@ RXR_DATA[55] $end
$var reg 1 (A RXR_DATA[54] $end
$var reg 1 (B RXR_DATA[53] $end
$var reg 1 (C RXR_DATA[52] $end
$var reg 1 (D RXR_DATA[51] $end
$var reg 1 (E RXR_DATA[50] $end
$var reg 1 (F RXR_DATA[49] $end
$var reg 1 (G RXR_DATA[48] $end
$var reg 1 (H RXR_DATA[47] $end
$var reg 1 (I RXR_DATA[46] $end
$var reg 1 (J RXR_DATA[45] $end
$var reg 1 (K RXR_DATA[44] $end
$var reg 1 (L RXR_DATA[43] $end
$var reg 1 (M RXR_DATA[42] $end
$var reg 1 (N RXR_DATA[41] $end
$var reg 1 (O RXR_DATA[40] $end
$var reg 1 (P RXR_DATA[39] $end
$var reg 1 (Q RXR_DATA[38] $end
$var reg 1 (R RXR_DATA[37] $end
$var reg 1 (S RXR_DATA[36] $end
$var reg 1 (T RXR_DATA[35] $end
$var reg 1 (U RXR_DATA[34] $end
$var reg 1 (V RXR_DATA[33] $end
$var reg 1 (W RXR_DATA[32] $end
$var reg 1 (X RXR_DATA[31] $end
$var reg 1 (Y RXR_DATA[30] $end
$var reg 1 (Z RXR_DATA[29] $end
$var reg 1 ([ RXR_DATA[28] $end
$var reg 1 (\ RXR_DATA[27] $end
$var reg 1 (] RXR_DATA[26] $end
$var reg 1 (^ RXR_DATA[25] $end
$var reg 1 (_ RXR_DATA[24] $end
$var reg 1 (` RXR_DATA[23] $end
$var reg 1 (a RXR_DATA[22] $end
$var reg 1 (b RXR_DATA[21] $end
$var reg 1 (c RXR_DATA[20] $end
$var reg 1 (d RXR_DATA[19] $end
$var reg 1 (e RXR_DATA[18] $end
$var reg 1 (f RXR_DATA[17] $end
$var reg 1 (g RXR_DATA[16] $end
$var reg 1 (h RXR_DATA[15] $end
$var reg 1 (i RXR_DATA[14] $end
$var reg 1 (j RXR_DATA[13] $end
$var reg 1 (k RXR_DATA[12] $end
$var reg 1 (l RXR_DATA[11] $end
$var reg 1 (m RXR_DATA[10] $end
$var reg 1 (n RXR_DATA[9] $end
$var reg 1 (o RXR_DATA[8] $end
$var reg 1 (p RXR_DATA[7] $end
$var reg 1 (q RXR_DATA[6] $end
$var reg 1 (r RXR_DATA[5] $end
$var reg 1 (s RXR_DATA[4] $end
$var reg 1 (t RXR_DATA[3] $end
$var reg 1 (u RXR_DATA[2] $end
$var reg 1 (v RXR_DATA[1] $end
$var reg 1 (w RXR_DATA[0] $end
$var reg 1 (x RXR_DATA_VALID $end
$var reg 1 (y RXR_DATA_WORD_ENABLE[3] $end
$var reg 1 (z RXR_DATA_WORD_ENABLE[2] $end
$var reg 1 ({ RXR_DATA_WORD_ENABLE[1] $end
$var reg 1 (| RXR_DATA_WORD_ENABLE[0] $end
$var reg 1 (} RXR_DATA_START_FLAG $end
$var reg 1 (~ RXR_DATA_START_OFFSET[1] $end
$var reg 1 )! RXR_DATA_START_OFFSET[0] $end
$var reg 1 )" RXR_DATA_END_FLAG $end
$var reg 1 )# RXR_DATA_END_OFFSET[1] $end
$var reg 1 )$ RXR_DATA_END_OFFSET[0] $end
$var reg 1 )% RXR_META_FDWBE[3] $end
$var reg 1 )& RXR_META_FDWBE[2] $end
$var reg 1 )' RXR_META_FDWBE[1] $end
$var reg 1 )( RXR_META_FDWBE[0] $end
$var reg 1 )) RXR_META_LDWBE[3] $end
$var reg 1 )* RXR_META_LDWBE[2] $end
$var reg 1 )+ RXR_META_LDWBE[1] $end
$var reg 1 ), RXR_META_LDWBE[0] $end
$var reg 1 )- RXR_META_TC[2] $end
$var reg 1 ). RXR_META_TC[1] $end
$var reg 1 )/ RXR_META_TC[0] $end
$var reg 1 )0 RXR_META_ATTR[2] $end
$var reg 1 )1 RXR_META_ATTR[1] $end
$var reg 1 )2 RXR_META_ATTR[0] $end
$var reg 1 )3 RXR_META_TAG[7] $end
$var reg 1 )4 RXR_META_TAG[6] $end
$var reg 1 )5 RXR_META_TAG[5] $end
$var reg 1 )6 RXR_META_TAG[4] $end
$var reg 1 )7 RXR_META_TAG[3] $end
$var reg 1 )8 RXR_META_TAG[2] $end
$var reg 1 )9 RXR_META_TAG[1] $end
$var reg 1 ): RXR_META_TAG[0] $end
$var reg 1 ); RXR_META_TYPE[2] $end
$var reg 1 )< RXR_META_TYPE[1] $end
$var reg 1 )= RXR_META_TYPE[0] $end
$var reg 1 )> RXR_META_ADDR[63] $end
$var reg 1 )? RXR_META_ADDR[62] $end
$var reg 1 )@ RXR_META_ADDR[61] $end
$var reg 1 )A RXR_META_ADDR[60] $end
$var reg 1 )B RXR_META_ADDR[59] $end
$var reg 1 )C RXR_META_ADDR[58] $end
$var reg 1 )D RXR_META_ADDR[57] $end
$var reg 1 )E RXR_META_ADDR[56] $end
$var reg 1 )F RXR_META_ADDR[55] $end
$var reg 1 )G RXR_META_ADDR[54] $end
$var reg 1 )H RXR_META_ADDR[53] $end
$var reg 1 )I RXR_META_ADDR[52] $end
$var reg 1 )J RXR_META_ADDR[51] $end
$var reg 1 )K RXR_META_ADDR[50] $end
$var reg 1 )L RXR_META_ADDR[49] $end
$var reg 1 )M RXR_META_ADDR[48] $end
$var reg 1 )N RXR_META_ADDR[47] $end
$var reg 1 )O RXR_META_ADDR[46] $end
$var reg 1 )P RXR_META_ADDR[45] $end
$var reg 1 )Q RXR_META_ADDR[44] $end
$var reg 1 )R RXR_META_ADDR[43] $end
$var reg 1 )S RXR_META_ADDR[42] $end
$var reg 1 )T RXR_META_ADDR[41] $end
$var reg 1 )U RXR_META_ADDR[40] $end
$var reg 1 )V RXR_META_ADDR[39] $end
$var reg 1 )W RXR_META_ADDR[38] $end
$var reg 1 )X RXR_META_ADDR[37] $end
$var reg 1 )Y RXR_META_ADDR[36] $end
$var reg 1 )Z RXR_META_ADDR[35] $end
$var reg 1 )[ RXR_META_ADDR[34] $end
$var reg 1 )\ RXR_META_ADDR[33] $end
$var reg 1 )] RXR_META_ADDR[32] $end
$var reg 1 )^ RXR_META_ADDR[31] $end
$var reg 1 )_ RXR_META_ADDR[30] $end
$var reg 1 )` RXR_META_ADDR[29] $end
$var reg 1 )a RXR_META_ADDR[28] $end
$var reg 1 )b RXR_META_ADDR[27] $end
$var reg 1 )c RXR_META_ADDR[26] $end
$var reg 1 )d RXR_META_ADDR[25] $end
$var reg 1 )e RXR_META_ADDR[24] $end
$var reg 1 )f RXR_META_ADDR[23] $end
$var reg 1 )g RXR_META_ADDR[22] $end
$var reg 1 )h RXR_META_ADDR[21] $end
$var reg 1 )i RXR_META_ADDR[20] $end
$var reg 1 )j RXR_META_ADDR[19] $end
$var reg 1 )k RXR_META_ADDR[18] $end
$var reg 1 )l RXR_META_ADDR[17] $end
$var reg 1 )m RXR_META_ADDR[16] $end
$var reg 1 )n RXR_META_ADDR[15] $end
$var reg 1 )o RXR_META_ADDR[14] $end
$var reg 1 )p RXR_META_ADDR[13] $end
$var reg 1 )q RXR_META_ADDR[12] $end
$var reg 1 )r RXR_META_ADDR[11] $end
$var reg 1 )s RXR_META_ADDR[10] $end
$var reg 1 )t RXR_META_ADDR[9] $end
$var reg 1 )u RXR_META_ADDR[8] $end
$var reg 1 )v RXR_META_ADDR[7] $end
$var reg 1 )w RXR_META_ADDR[6] $end
$var reg 1 )x RXR_META_ADDR[5] $end
$var reg 1 )y RXR_META_ADDR[4] $end
$var reg 1 )z RXR_META_ADDR[3] $end
$var reg 1 ){ RXR_META_ADDR[2] $end
$var reg 1 )| RXR_META_ADDR[1] $end
$var reg 1 )} RXR_META_ADDR[0] $end
$var reg 1 )~ RXR_META_BAR_DECODED[7] $end
$var reg 1 *! RXR_META_BAR_DECODED[6] $end
$var reg 1 *" RXR_META_BAR_DECODED[5] $end
$var reg 1 *# RXR_META_BAR_DECODED[4] $end
$var reg 1 *$ RXR_META_BAR_DECODED[3] $end
$var reg 1 *% RXR_META_BAR_DECODED[2] $end
$var reg 1 *& RXR_META_BAR_DECODED[1] $end
$var reg 1 *' RXR_META_BAR_DECODED[0] $end
$var reg 1 *( RXR_META_REQUESTER_ID[15] $end
$var reg 1 *) RXR_META_REQUESTER_ID[14] $end
$var reg 1 ** RXR_META_REQUESTER_ID[13] $end
$var reg 1 *+ RXR_META_REQUESTER_ID[12] $end
$var reg 1 *, RXR_META_REQUESTER_ID[11] $end
$var reg 1 *- RXR_META_REQUESTER_ID[10] $end
$var reg 1 *. RXR_META_REQUESTER_ID[9] $end
$var reg 1 */ RXR_META_REQUESTER_ID[8] $end
$var reg 1 *0 RXR_META_REQUESTER_ID[7] $end
$var reg 1 *1 RXR_META_REQUESTER_ID[6] $end
$var reg 1 *2 RXR_META_REQUESTER_ID[5] $end
$var reg 1 *3 RXR_META_REQUESTER_ID[4] $end
$var reg 1 *4 RXR_META_REQUESTER_ID[3] $end
$var reg 1 *5 RXR_META_REQUESTER_ID[2] $end
$var reg 1 *6 RXR_META_REQUESTER_ID[1] $end
$var reg 1 *7 RXR_META_REQUESTER_ID[0] $end
$var reg 1 *8 RXR_META_LENGTH[9] $end
$var reg 1 *9 RXR_META_LENGTH[8] $end
$var reg 1 *: RXR_META_LENGTH[7] $end
$var reg 1 *; RXR_META_LENGTH[6] $end
$var reg 1 *< RXR_META_LENGTH[5] $end
$var reg 1 *= RXR_META_LENGTH[4] $end
$var reg 1 *> RXR_META_LENGTH[3] $end
$var reg 1 *? RXR_META_LENGTH[2] $end
$var reg 1 *@ RXR_META_LENGTH[1] $end
$var reg 1 *A RXR_META_LENGTH[0] $end
$var reg 1 *B RXR_META_EP $end
$var reg 1 *C RX_SR_DATA[639] $end
$var reg 1 *D RX_SR_DATA[638] $end
$var reg 1 *E RX_SR_DATA[637] $end
$var reg 1 *F RX_SR_DATA[636] $end
$var reg 1 *G RX_SR_DATA[635] $end
$var reg 1 *H RX_SR_DATA[634] $end
$var reg 1 *I RX_SR_DATA[633] $end
$var reg 1 *J RX_SR_DATA[632] $end
$var reg 1 *K RX_SR_DATA[631] $end
$var reg 1 *L RX_SR_DATA[630] $end
$var reg 1 *M RX_SR_DATA[629] $end
$var reg 1 *N RX_SR_DATA[628] $end
$var reg 1 *O RX_SR_DATA[627] $end
$var reg 1 *P RX_SR_DATA[626] $end
$var reg 1 *Q RX_SR_DATA[625] $end
$var reg 1 *R RX_SR_DATA[624] $end
$var reg 1 *S RX_SR_DATA[623] $end
$var reg 1 *T RX_SR_DATA[622] $end
$var reg 1 *U RX_SR_DATA[621] $end
$var reg 1 *V RX_SR_DATA[620] $end
$var reg 1 *W RX_SR_DATA[619] $end
$var reg 1 *X RX_SR_DATA[618] $end
$var reg 1 *Y RX_SR_DATA[617] $end
$var reg 1 *Z RX_SR_DATA[616] $end
$var reg 1 *[ RX_SR_DATA[615] $end
$var reg 1 *\ RX_SR_DATA[614] $end
$var reg 1 *] RX_SR_DATA[613] $end
$var reg 1 *^ RX_SR_DATA[612] $end
$var reg 1 *_ RX_SR_DATA[611] $end
$var reg 1 *` RX_SR_DATA[610] $end
$var reg 1 *a RX_SR_DATA[609] $end
$var reg 1 *b RX_SR_DATA[608] $end
$var reg 1 *c RX_SR_DATA[607] $end
$var reg 1 *d RX_SR_DATA[606] $end
$var reg 1 *e RX_SR_DATA[605] $end
$var reg 1 *f RX_SR_DATA[604] $end
$var reg 1 *g RX_SR_DATA[603] $end
$var reg 1 *h RX_SR_DATA[602] $end
$var reg 1 *i RX_SR_DATA[601] $end
$var reg 1 *j RX_SR_DATA[600] $end
$var reg 1 *k RX_SR_DATA[599] $end
$var reg 1 *l RX_SR_DATA[598] $end
$var reg 1 *m RX_SR_DATA[597] $end
$var reg 1 *n RX_SR_DATA[596] $end
$var reg 1 *o RX_SR_DATA[595] $end
$var reg 1 *p RX_SR_DATA[594] $end
$var reg 1 *q RX_SR_DATA[593] $end
$var reg 1 *r RX_SR_DATA[592] $end
$var reg 1 *s RX_SR_DATA[591] $end
$var reg 1 *t RX_SR_DATA[590] $end
$var reg 1 *u RX_SR_DATA[589] $end
$var reg 1 *v RX_SR_DATA[588] $end
$var reg 1 *w RX_SR_DATA[587] $end
$var reg 1 *x RX_SR_DATA[586] $end
$var reg 1 *y RX_SR_DATA[585] $end
$var reg 1 *z RX_SR_DATA[584] $end
$var reg 1 *{ RX_SR_DATA[583] $end
$var reg 1 *| RX_SR_DATA[582] $end
$var reg 1 *} RX_SR_DATA[581] $end
$var reg 1 *~ RX_SR_DATA[580] $end
$var reg 1 +! RX_SR_DATA[579] $end
$var reg 1 +" RX_SR_DATA[578] $end
$var reg 1 +# RX_SR_DATA[577] $end
$var reg 1 +$ RX_SR_DATA[576] $end
$var reg 1 +% RX_SR_DATA[575] $end
$var reg 1 +& RX_SR_DATA[574] $end
$var reg 1 +' RX_SR_DATA[573] $end
$var reg 1 +( RX_SR_DATA[572] $end
$var reg 1 +) RX_SR_DATA[571] $end
$var reg 1 +* RX_SR_DATA[570] $end
$var reg 1 ++ RX_SR_DATA[569] $end
$var reg 1 +, RX_SR_DATA[568] $end
$var reg 1 +- RX_SR_DATA[567] $end
$var reg 1 +. RX_SR_DATA[566] $end
$var reg 1 +/ RX_SR_DATA[565] $end
$var reg 1 +0 RX_SR_DATA[564] $end
$var reg 1 +1 RX_SR_DATA[563] $end
$var reg 1 +2 RX_SR_DATA[562] $end
$var reg 1 +3 RX_SR_DATA[561] $end
$var reg 1 +4 RX_SR_DATA[560] $end
$var reg 1 +5 RX_SR_DATA[559] $end
$var reg 1 +6 RX_SR_DATA[558] $end
$var reg 1 +7 RX_SR_DATA[557] $end
$var reg 1 +8 RX_SR_DATA[556] $end
$var reg 1 +9 RX_SR_DATA[555] $end
$var reg 1 +: RX_SR_DATA[554] $end
$var reg 1 +; RX_SR_DATA[553] $end
$var reg 1 +< RX_SR_DATA[552] $end
$var reg 1 += RX_SR_DATA[551] $end
$var reg 1 +> RX_SR_DATA[550] $end
$var reg 1 +? RX_SR_DATA[549] $end
$var reg 1 +@ RX_SR_DATA[548] $end
$var reg 1 +A RX_SR_DATA[547] $end
$var reg 1 +B RX_SR_DATA[546] $end
$var reg 1 +C RX_SR_DATA[545] $end
$var reg 1 +D RX_SR_DATA[544] $end
$var reg 1 +E RX_SR_DATA[543] $end
$var reg 1 +F RX_SR_DATA[542] $end
$var reg 1 +G RX_SR_DATA[541] $end
$var reg 1 +H RX_SR_DATA[540] $end
$var reg 1 +I RX_SR_DATA[539] $end
$var reg 1 +J RX_SR_DATA[538] $end
$var reg 1 +K RX_SR_DATA[537] $end
$var reg 1 +L RX_SR_DATA[536] $end
$var reg 1 +M RX_SR_DATA[535] $end
$var reg 1 +N RX_SR_DATA[534] $end
$var reg 1 +O RX_SR_DATA[533] $end
$var reg 1 +P RX_SR_DATA[532] $end
$var reg 1 +Q RX_SR_DATA[531] $end
$var reg 1 +R RX_SR_DATA[530] $end
$var reg 1 +S RX_SR_DATA[529] $end
$var reg 1 +T RX_SR_DATA[528] $end
$var reg 1 +U RX_SR_DATA[527] $end
$var reg 1 +V RX_SR_DATA[526] $end
$var reg 1 +W RX_SR_DATA[525] $end
$var reg 1 +X RX_SR_DATA[524] $end
$var reg 1 +Y RX_SR_DATA[523] $end
$var reg 1 +Z RX_SR_DATA[522] $end
$var reg 1 +[ RX_SR_DATA[521] $end
$var reg 1 +\ RX_SR_DATA[520] $end
$var reg 1 +] RX_SR_DATA[519] $end
$var reg 1 +^ RX_SR_DATA[518] $end
$var reg 1 +_ RX_SR_DATA[517] $end
$var reg 1 +` RX_SR_DATA[516] $end
$var reg 1 +a RX_SR_DATA[515] $end
$var reg 1 +b RX_SR_DATA[514] $end
$var reg 1 +c RX_SR_DATA[513] $end
$var reg 1 +d RX_SR_DATA[512] $end
$var reg 1 +e RX_SR_DATA[511] $end
$var reg 1 +f RX_SR_DATA[510] $end
$var reg 1 +g RX_SR_DATA[509] $end
$var reg 1 +h RX_SR_DATA[508] $end
$var reg 1 +i RX_SR_DATA[507] $end
$var reg 1 +j RX_SR_DATA[506] $end
$var reg 1 +k RX_SR_DATA[505] $end
$var reg 1 +l RX_SR_DATA[504] $end
$var reg 1 +m RX_SR_DATA[503] $end
$var reg 1 +n RX_SR_DATA[502] $end
$var reg 1 +o RX_SR_DATA[501] $end
$var reg 1 +p RX_SR_DATA[500] $end
$var reg 1 +q RX_SR_DATA[499] $end
$var reg 1 +r RX_SR_DATA[498] $end
$var reg 1 +s RX_SR_DATA[497] $end
$var reg 1 +t RX_SR_DATA[496] $end
$var reg 1 +u RX_SR_DATA[495] $end
$var reg 1 +v RX_SR_DATA[494] $end
$var reg 1 +w RX_SR_DATA[493] $end
$var reg 1 +x RX_SR_DATA[492] $end
$var reg 1 +y RX_SR_DATA[491] $end
$var reg 1 +z RX_SR_DATA[490] $end
$var reg 1 +{ RX_SR_DATA[489] $end
$var reg 1 +| RX_SR_DATA[488] $end
$var reg 1 +} RX_SR_DATA[487] $end
$var reg 1 +~ RX_SR_DATA[486] $end
$var reg 1 ,! RX_SR_DATA[485] $end
$var reg 1 ," RX_SR_DATA[484] $end
$var reg 1 ,# RX_SR_DATA[483] $end
$var reg 1 ,$ RX_SR_DATA[482] $end
$var reg 1 ,% RX_SR_DATA[481] $end
$var reg 1 ,& RX_SR_DATA[480] $end
$var reg 1 ,' RX_SR_DATA[479] $end
$var reg 1 ,( RX_SR_DATA[478] $end
$var reg 1 ,) RX_SR_DATA[477] $end
$var reg 1 ,* RX_SR_DATA[476] $end
$var reg 1 ,+ RX_SR_DATA[475] $end
$var reg 1 ,, RX_SR_DATA[474] $end
$var reg 1 ,- RX_SR_DATA[473] $end
$var reg 1 ,. RX_SR_DATA[472] $end
$var reg 1 ,/ RX_SR_DATA[471] $end
$var reg 1 ,0 RX_SR_DATA[470] $end
$var reg 1 ,1 RX_SR_DATA[469] $end
$var reg 1 ,2 RX_SR_DATA[468] $end
$var reg 1 ,3 RX_SR_DATA[467] $end
$var reg 1 ,4 RX_SR_DATA[466] $end
$var reg 1 ,5 RX_SR_DATA[465] $end
$var reg 1 ,6 RX_SR_DATA[464] $end
$var reg 1 ,7 RX_SR_DATA[463] $end
$var reg 1 ,8 RX_SR_DATA[462] $end
$var reg 1 ,9 RX_SR_DATA[461] $end
$var reg 1 ,: RX_SR_DATA[460] $end
$var reg 1 ,; RX_SR_DATA[459] $end
$var reg 1 ,< RX_SR_DATA[458] $end
$var reg 1 ,= RX_SR_DATA[457] $end
$var reg 1 ,> RX_SR_DATA[456] $end
$var reg 1 ,? RX_SR_DATA[455] $end
$var reg 1 ,@ RX_SR_DATA[454] $end
$var reg 1 ,A RX_SR_DATA[453] $end
$var reg 1 ,B RX_SR_DATA[452] $end
$var reg 1 ,C RX_SR_DATA[451] $end
$var reg 1 ,D RX_SR_DATA[450] $end
$var reg 1 ,E RX_SR_DATA[449] $end
$var reg 1 ,F RX_SR_DATA[448] $end
$var reg 1 ,G RX_SR_DATA[447] $end
$var reg 1 ,H RX_SR_DATA[446] $end
$var reg 1 ,I RX_SR_DATA[445] $end
$var reg 1 ,J RX_SR_DATA[444] $end
$var reg 1 ,K RX_SR_DATA[443] $end
$var reg 1 ,L RX_SR_DATA[442] $end
$var reg 1 ,M RX_SR_DATA[441] $end
$var reg 1 ,N RX_SR_DATA[440] $end
$var reg 1 ,O RX_SR_DATA[439] $end
$var reg 1 ,P RX_SR_DATA[438] $end
$var reg 1 ,Q RX_SR_DATA[437] $end
$var reg 1 ,R RX_SR_DATA[436] $end
$var reg 1 ,S RX_SR_DATA[435] $end
$var reg 1 ,T RX_SR_DATA[434] $end
$var reg 1 ,U RX_SR_DATA[433] $end
$var reg 1 ,V RX_SR_DATA[432] $end
$var reg 1 ,W RX_SR_DATA[431] $end
$var reg 1 ,X RX_SR_DATA[430] $end
$var reg 1 ,Y RX_SR_DATA[429] $end
$var reg 1 ,Z RX_SR_DATA[428] $end
$var reg 1 ,[ RX_SR_DATA[427] $end
$var reg 1 ,\ RX_SR_DATA[426] $end
$var reg 1 ,] RX_SR_DATA[425] $end
$var reg 1 ,^ RX_SR_DATA[424] $end
$var reg 1 ,_ RX_SR_DATA[423] $end
$var reg 1 ,` RX_SR_DATA[422] $end
$var reg 1 ,a RX_SR_DATA[421] $end
$var reg 1 ,b RX_SR_DATA[420] $end
$var reg 1 ,c RX_SR_DATA[419] $end
$var reg 1 ,d RX_SR_DATA[418] $end
$var reg 1 ,e RX_SR_DATA[417] $end
$var reg 1 ,f RX_SR_DATA[416] $end
$var reg 1 ,g RX_SR_DATA[415] $end
$var reg 1 ,h RX_SR_DATA[414] $end
$var reg 1 ,i RX_SR_DATA[413] $end
$var reg 1 ,j RX_SR_DATA[412] $end
$var reg 1 ,k RX_SR_DATA[411] $end
$var reg 1 ,l RX_SR_DATA[410] $end
$var reg 1 ,m RX_SR_DATA[409] $end
$var reg 1 ,n RX_SR_DATA[408] $end
$var reg 1 ,o RX_SR_DATA[407] $end
$var reg 1 ,p RX_SR_DATA[406] $end
$var reg 1 ,q RX_SR_DATA[405] $end
$var reg 1 ,r RX_SR_DATA[404] $end
$var reg 1 ,s RX_SR_DATA[403] $end
$var reg 1 ,t RX_SR_DATA[402] $end
$var reg 1 ,u RX_SR_DATA[401] $end
$var reg 1 ,v RX_SR_DATA[400] $end
$var reg 1 ,w RX_SR_DATA[399] $end
$var reg 1 ,x RX_SR_DATA[398] $end
$var reg 1 ,y RX_SR_DATA[397] $end
$var reg 1 ,z RX_SR_DATA[396] $end
$var reg 1 ,{ RX_SR_DATA[395] $end
$var reg 1 ,| RX_SR_DATA[394] $end
$var reg 1 ,} RX_SR_DATA[393] $end
$var reg 1 ,~ RX_SR_DATA[392] $end
$var reg 1 -! RX_SR_DATA[391] $end
$var reg 1 -" RX_SR_DATA[390] $end
$var reg 1 -# RX_SR_DATA[389] $end
$var reg 1 -$ RX_SR_DATA[388] $end
$var reg 1 -% RX_SR_DATA[387] $end
$var reg 1 -& RX_SR_DATA[386] $end
$var reg 1 -' RX_SR_DATA[385] $end
$var reg 1 -( RX_SR_DATA[384] $end
$var reg 1 -) RX_SR_DATA[383] $end
$var reg 1 -* RX_SR_DATA[382] $end
$var reg 1 -+ RX_SR_DATA[381] $end
$var reg 1 -, RX_SR_DATA[380] $end
$var reg 1 -- RX_SR_DATA[379] $end
$var reg 1 -. RX_SR_DATA[378] $end
$var reg 1 -/ RX_SR_DATA[377] $end
$var reg 1 -0 RX_SR_DATA[376] $end
$var reg 1 -1 RX_SR_DATA[375] $end
$var reg 1 -2 RX_SR_DATA[374] $end
$var reg 1 -3 RX_SR_DATA[373] $end
$var reg 1 -4 RX_SR_DATA[372] $end
$var reg 1 -5 RX_SR_DATA[371] $end
$var reg 1 -6 RX_SR_DATA[370] $end
$var reg 1 -7 RX_SR_DATA[369] $end
$var reg 1 -8 RX_SR_DATA[368] $end
$var reg 1 -9 RX_SR_DATA[367] $end
$var reg 1 -: RX_SR_DATA[366] $end
$var reg 1 -; RX_SR_DATA[365] $end
$var reg 1 -< RX_SR_DATA[364] $end
$var reg 1 -= RX_SR_DATA[363] $end
$var reg 1 -> RX_SR_DATA[362] $end
$var reg 1 -? RX_SR_DATA[361] $end
$var reg 1 -@ RX_SR_DATA[360] $end
$var reg 1 -A RX_SR_DATA[359] $end
$var reg 1 -B RX_SR_DATA[358] $end
$var reg 1 -C RX_SR_DATA[357] $end
$var reg 1 -D RX_SR_DATA[356] $end
$var reg 1 -E RX_SR_DATA[355] $end
$var reg 1 -F RX_SR_DATA[354] $end
$var reg 1 -G RX_SR_DATA[353] $end
$var reg 1 -H RX_SR_DATA[352] $end
$var reg 1 -I RX_SR_DATA[351] $end
$var reg 1 -J RX_SR_DATA[350] $end
$var reg 1 -K RX_SR_DATA[349] $end
$var reg 1 -L RX_SR_DATA[348] $end
$var reg 1 -M RX_SR_DATA[347] $end
$var reg 1 -N RX_SR_DATA[346] $end
$var reg 1 -O RX_SR_DATA[345] $end
$var reg 1 -P RX_SR_DATA[344] $end
$var reg 1 -Q RX_SR_DATA[343] $end
$var reg 1 -R RX_SR_DATA[342] $end
$var reg 1 -S RX_SR_DATA[341] $end
$var reg 1 -T RX_SR_DATA[340] $end
$var reg 1 -U RX_SR_DATA[339] $end
$var reg 1 -V RX_SR_DATA[338] $end
$var reg 1 -W RX_SR_DATA[337] $end
$var reg 1 -X RX_SR_DATA[336] $end
$var reg 1 -Y RX_SR_DATA[335] $end
$var reg 1 -Z RX_SR_DATA[334] $end
$var reg 1 -[ RX_SR_DATA[333] $end
$var reg 1 -\ RX_SR_DATA[332] $end
$var reg 1 -] RX_SR_DATA[331] $end
$var reg 1 -^ RX_SR_DATA[330] $end
$var reg 1 -_ RX_SR_DATA[329] $end
$var reg 1 -` RX_SR_DATA[328] $end
$var reg 1 -a RX_SR_DATA[327] $end
$var reg 1 -b RX_SR_DATA[326] $end
$var reg 1 -c RX_SR_DATA[325] $end
$var reg 1 -d RX_SR_DATA[324] $end
$var reg 1 -e RX_SR_DATA[323] $end
$var reg 1 -f RX_SR_DATA[322] $end
$var reg 1 -g RX_SR_DATA[321] $end
$var reg 1 -h RX_SR_DATA[320] $end
$var reg 1 -i RX_SR_DATA[319] $end
$var reg 1 -j RX_SR_DATA[318] $end
$var reg 1 -k RX_SR_DATA[317] $end
$var reg 1 -l RX_SR_DATA[316] $end
$var reg 1 -m RX_SR_DATA[315] $end
$var reg 1 -n RX_SR_DATA[314] $end
$var reg 1 -o RX_SR_DATA[313] $end
$var reg 1 -p RX_SR_DATA[312] $end
$var reg 1 -q RX_SR_DATA[311] $end
$var reg 1 -r RX_SR_DATA[310] $end
$var reg 1 -s RX_SR_DATA[309] $end
$var reg 1 -t RX_SR_DATA[308] $end
$var reg 1 -u RX_SR_DATA[307] $end
$var reg 1 -v RX_SR_DATA[306] $end
$var reg 1 -w RX_SR_DATA[305] $end
$var reg 1 -x RX_SR_DATA[304] $end
$var reg 1 -y RX_SR_DATA[303] $end
$var reg 1 -z RX_SR_DATA[302] $end
$var reg 1 -{ RX_SR_DATA[301] $end
$var reg 1 -| RX_SR_DATA[300] $end
$var reg 1 -} RX_SR_DATA[299] $end
$var reg 1 -~ RX_SR_DATA[298] $end
$var reg 1 .! RX_SR_DATA[297] $end
$var reg 1 ." RX_SR_DATA[296] $end
$var reg 1 .# RX_SR_DATA[295] $end
$var reg 1 .$ RX_SR_DATA[294] $end
$var reg 1 .% RX_SR_DATA[293] $end
$var reg 1 .& RX_SR_DATA[292] $end
$var reg 1 .' RX_SR_DATA[291] $end
$var reg 1 .( RX_SR_DATA[290] $end
$var reg 1 .) RX_SR_DATA[289] $end
$var reg 1 .* RX_SR_DATA[288] $end
$var reg 1 .+ RX_SR_DATA[287] $end
$var reg 1 ., RX_SR_DATA[286] $end
$var reg 1 .- RX_SR_DATA[285] $end
$var reg 1 .. RX_SR_DATA[284] $end
$var reg 1 ./ RX_SR_DATA[283] $end
$var reg 1 .0 RX_SR_DATA[282] $end
$var reg 1 .1 RX_SR_DATA[281] $end
$var reg 1 .2 RX_SR_DATA[280] $end
$var reg 1 .3 RX_SR_DATA[279] $end
$var reg 1 .4 RX_SR_DATA[278] $end
$var reg 1 .5 RX_SR_DATA[277] $end
$var reg 1 .6 RX_SR_DATA[276] $end
$var reg 1 .7 RX_SR_DATA[275] $end
$var reg 1 .8 RX_SR_DATA[274] $end
$var reg 1 .9 RX_SR_DATA[273] $end
$var reg 1 .: RX_SR_DATA[272] $end
$var reg 1 .; RX_SR_DATA[271] $end
$var reg 1 .< RX_SR_DATA[270] $end
$var reg 1 .= RX_SR_DATA[269] $end
$var reg 1 .> RX_SR_DATA[268] $end
$var reg 1 .? RX_SR_DATA[267] $end
$var reg 1 .@ RX_SR_DATA[266] $end
$var reg 1 .A RX_SR_DATA[265] $end
$var reg 1 .B RX_SR_DATA[264] $end
$var reg 1 .C RX_SR_DATA[263] $end
$var reg 1 .D RX_SR_DATA[262] $end
$var reg 1 .E RX_SR_DATA[261] $end
$var reg 1 .F RX_SR_DATA[260] $end
$var reg 1 .G RX_SR_DATA[259] $end
$var reg 1 .H RX_SR_DATA[258] $end
$var reg 1 .I RX_SR_DATA[257] $end
$var reg 1 .J RX_SR_DATA[256] $end
$var reg 1 .K RX_SR_DATA[255] $end
$var reg 1 .L RX_SR_DATA[254] $end
$var reg 1 .M RX_SR_DATA[253] $end
$var reg 1 .N RX_SR_DATA[252] $end
$var reg 1 .O RX_SR_DATA[251] $end
$var reg 1 .P RX_SR_DATA[250] $end
$var reg 1 .Q RX_SR_DATA[249] $end
$var reg 1 .R RX_SR_DATA[248] $end
$var reg 1 .S RX_SR_DATA[247] $end
$var reg 1 .T RX_SR_DATA[246] $end
$var reg 1 .U RX_SR_DATA[245] $end
$var reg 1 .V RX_SR_DATA[244] $end
$var reg 1 .W RX_SR_DATA[243] $end
$var reg 1 .X RX_SR_DATA[242] $end
$var reg 1 .Y RX_SR_DATA[241] $end
$var reg 1 .Z RX_SR_DATA[240] $end
$var reg 1 .[ RX_SR_DATA[239] $end
$var reg 1 .\ RX_SR_DATA[238] $end
$var reg 1 .] RX_SR_DATA[237] $end
$var reg 1 .^ RX_SR_DATA[236] $end
$var reg 1 ._ RX_SR_DATA[235] $end
$var reg 1 .` RX_SR_DATA[234] $end
$var reg 1 .a RX_SR_DATA[233] $end
$var reg 1 .b RX_SR_DATA[232] $end
$var reg 1 .c RX_SR_DATA[231] $end
$var reg 1 .d RX_SR_DATA[230] $end
$var reg 1 .e RX_SR_DATA[229] $end
$var reg 1 .f RX_SR_DATA[228] $end
$var reg 1 .g RX_SR_DATA[227] $end
$var reg 1 .h RX_SR_DATA[226] $end
$var reg 1 .i RX_SR_DATA[225] $end
$var reg 1 .j RX_SR_DATA[224] $end
$var reg 1 .k RX_SR_DATA[223] $end
$var reg 1 .l RX_SR_DATA[222] $end
$var reg 1 .m RX_SR_DATA[221] $end
$var reg 1 .n RX_SR_DATA[220] $end
$var reg 1 .o RX_SR_DATA[219] $end
$var reg 1 .p RX_SR_DATA[218] $end
$var reg 1 .q RX_SR_DATA[217] $end
$var reg 1 .r RX_SR_DATA[216] $end
$var reg 1 .s RX_SR_DATA[215] $end
$var reg 1 .t RX_SR_DATA[214] $end
$var reg 1 .u RX_SR_DATA[213] $end
$var reg 1 .v RX_SR_DATA[212] $end
$var reg 1 .w RX_SR_DATA[211] $end
$var reg 1 .x RX_SR_DATA[210] $end
$var reg 1 .y RX_SR_DATA[209] $end
$var reg 1 .z RX_SR_DATA[208] $end
$var reg 1 .{ RX_SR_DATA[207] $end
$var reg 1 .| RX_SR_DATA[206] $end
$var reg 1 .} RX_SR_DATA[205] $end
$var reg 1 .~ RX_SR_DATA[204] $end
$var reg 1 /! RX_SR_DATA[203] $end
$var reg 1 /" RX_SR_DATA[202] $end
$var reg 1 /# RX_SR_DATA[201] $end
$var reg 1 /$ RX_SR_DATA[200] $end
$var reg 1 /% RX_SR_DATA[199] $end
$var reg 1 /& RX_SR_DATA[198] $end
$var reg 1 /' RX_SR_DATA[197] $end
$var reg 1 /( RX_SR_DATA[196] $end
$var reg 1 /) RX_SR_DATA[195] $end
$var reg 1 /* RX_SR_DATA[194] $end
$var reg 1 /+ RX_SR_DATA[193] $end
$var reg 1 /, RX_SR_DATA[192] $end
$var reg 1 /- RX_SR_DATA[191] $end
$var reg 1 /. RX_SR_DATA[190] $end
$var reg 1 // RX_SR_DATA[189] $end
$var reg 1 /0 RX_SR_DATA[188] $end
$var reg 1 /1 RX_SR_DATA[187] $end
$var reg 1 /2 RX_SR_DATA[186] $end
$var reg 1 /3 RX_SR_DATA[185] $end
$var reg 1 /4 RX_SR_DATA[184] $end
$var reg 1 /5 RX_SR_DATA[183] $end
$var reg 1 /6 RX_SR_DATA[182] $end
$var reg 1 /7 RX_SR_DATA[181] $end
$var reg 1 /8 RX_SR_DATA[180] $end
$var reg 1 /9 RX_SR_DATA[179] $end
$var reg 1 /: RX_SR_DATA[178] $end
$var reg 1 /; RX_SR_DATA[177] $end
$var reg 1 /< RX_SR_DATA[176] $end
$var reg 1 /= RX_SR_DATA[175] $end
$var reg 1 /> RX_SR_DATA[174] $end
$var reg 1 /? RX_SR_DATA[173] $end
$var reg 1 /@ RX_SR_DATA[172] $end
$var reg 1 /A RX_SR_DATA[171] $end
$var reg 1 /B RX_SR_DATA[170] $end
$var reg 1 /C RX_SR_DATA[169] $end
$var reg 1 /D RX_SR_DATA[168] $end
$var reg 1 /E RX_SR_DATA[167] $end
$var reg 1 /F RX_SR_DATA[166] $end
$var reg 1 /G RX_SR_DATA[165] $end
$var reg 1 /H RX_SR_DATA[164] $end
$var reg 1 /I RX_SR_DATA[163] $end
$var reg 1 /J RX_SR_DATA[162] $end
$var reg 1 /K RX_SR_DATA[161] $end
$var reg 1 /L RX_SR_DATA[160] $end
$var reg 1 /M RX_SR_DATA[159] $end
$var reg 1 /N RX_SR_DATA[158] $end
$var reg 1 /O RX_SR_DATA[157] $end
$var reg 1 /P RX_SR_DATA[156] $end
$var reg 1 /Q RX_SR_DATA[155] $end
$var reg 1 /R RX_SR_DATA[154] $end
$var reg 1 /S RX_SR_DATA[153] $end
$var reg 1 /T RX_SR_DATA[152] $end
$var reg 1 /U RX_SR_DATA[151] $end
$var reg 1 /V RX_SR_DATA[150] $end
$var reg 1 /W RX_SR_DATA[149] $end
$var reg 1 /X RX_SR_DATA[148] $end
$var reg 1 /Y RX_SR_DATA[147] $end
$var reg 1 /Z RX_SR_DATA[146] $end
$var reg 1 /[ RX_SR_DATA[145] $end
$var reg 1 /\ RX_SR_DATA[144] $end
$var reg 1 /] RX_SR_DATA[143] $end
$var reg 1 /^ RX_SR_DATA[142] $end
$var reg 1 /_ RX_SR_DATA[141] $end
$var reg 1 /` RX_SR_DATA[140] $end
$var reg 1 /a RX_SR_DATA[139] $end
$var reg 1 /b RX_SR_DATA[138] $end
$var reg 1 /c RX_SR_DATA[137] $end
$var reg 1 /d RX_SR_DATA[136] $end
$var reg 1 /e RX_SR_DATA[135] $end
$var reg 1 /f RX_SR_DATA[134] $end
$var reg 1 /g RX_SR_DATA[133] $end
$var reg 1 /h RX_SR_DATA[132] $end
$var reg 1 /i RX_SR_DATA[131] $end
$var reg 1 /j RX_SR_DATA[130] $end
$var reg 1 /k RX_SR_DATA[129] $end
$var reg 1 /l RX_SR_DATA[128] $end
$var reg 1 /m RX_SR_DATA[127] $end
$var reg 1 /n RX_SR_DATA[126] $end
$var reg 1 /o RX_SR_DATA[125] $end
$var reg 1 /p RX_SR_DATA[124] $end
$var reg 1 /q RX_SR_DATA[123] $end
$var reg 1 /r RX_SR_DATA[122] $end
$var reg 1 /s RX_SR_DATA[121] $end
$var reg 1 /t RX_SR_DATA[120] $end
$var reg 1 /u RX_SR_DATA[119] $end
$var reg 1 /v RX_SR_DATA[118] $end
$var reg 1 /w RX_SR_DATA[117] $end
$var reg 1 /x RX_SR_DATA[116] $end
$var reg 1 /y RX_SR_DATA[115] $end
$var reg 1 /z RX_SR_DATA[114] $end
$var reg 1 /{ RX_SR_DATA[113] $end
$var reg 1 /| RX_SR_DATA[112] $end
$var reg 1 /} RX_SR_DATA[111] $end
$var reg 1 /~ RX_SR_DATA[110] $end
$var reg 1 0! RX_SR_DATA[109] $end
$var reg 1 0" RX_SR_DATA[108] $end
$var reg 1 0# RX_SR_DATA[107] $end
$var reg 1 0$ RX_SR_DATA[106] $end
$var reg 1 0% RX_SR_DATA[105] $end
$var reg 1 0& RX_SR_DATA[104] $end
$var reg 1 0' RX_SR_DATA[103] $end
$var reg 1 0( RX_SR_DATA[102] $end
$var reg 1 0) RX_SR_DATA[101] $end
$var reg 1 0* RX_SR_DATA[100] $end
$var reg 1 0+ RX_SR_DATA[99] $end
$var reg 1 0, RX_SR_DATA[98] $end
$var reg 1 0- RX_SR_DATA[97] $end
$var reg 1 0. RX_SR_DATA[96] $end
$var reg 1 0/ RX_SR_DATA[95] $end
$var reg 1 00 RX_SR_DATA[94] $end
$var reg 1 01 RX_SR_DATA[93] $end
$var reg 1 02 RX_SR_DATA[92] $end
$var reg 1 03 RX_SR_DATA[91] $end
$var reg 1 04 RX_SR_DATA[90] $end
$var reg 1 05 RX_SR_DATA[89] $end
$var reg 1 06 RX_SR_DATA[88] $end
$var reg 1 07 RX_SR_DATA[87] $end
$var reg 1 08 RX_SR_DATA[86] $end
$var reg 1 09 RX_SR_DATA[85] $end
$var reg 1 0: RX_SR_DATA[84] $end
$var reg 1 0; RX_SR_DATA[83] $end
$var reg 1 0< RX_SR_DATA[82] $end
$var reg 1 0= RX_SR_DATA[81] $end
$var reg 1 0> RX_SR_DATA[80] $end
$var reg 1 0? RX_SR_DATA[79] $end
$var reg 1 0@ RX_SR_DATA[78] $end
$var reg 1 0A RX_SR_DATA[77] $end
$var reg 1 0B RX_SR_DATA[76] $end
$var reg 1 0C RX_SR_DATA[75] $end
$var reg 1 0D RX_SR_DATA[74] $end
$var reg 1 0E RX_SR_DATA[73] $end
$var reg 1 0F RX_SR_DATA[72] $end
$var reg 1 0G RX_SR_DATA[71] $end
$var reg 1 0H RX_SR_DATA[70] $end
$var reg 1 0I RX_SR_DATA[69] $end
$var reg 1 0J RX_SR_DATA[68] $end
$var reg 1 0K RX_SR_DATA[67] $end
$var reg 1 0L RX_SR_DATA[66] $end
$var reg 1 0M RX_SR_DATA[65] $end
$var reg 1 0N RX_SR_DATA[64] $end
$var reg 1 0O RX_SR_DATA[63] $end
$var reg 1 0P RX_SR_DATA[62] $end
$var reg 1 0Q RX_SR_DATA[61] $end
$var reg 1 0R RX_SR_DATA[60] $end
$var reg 1 0S RX_SR_DATA[59] $end
$var reg 1 0T RX_SR_DATA[58] $end
$var reg 1 0U RX_SR_DATA[57] $end
$var reg 1 0V RX_SR_DATA[56] $end
$var reg 1 0W RX_SR_DATA[55] $end
$var reg 1 0X RX_SR_DATA[54] $end
$var reg 1 0Y RX_SR_DATA[53] $end
$var reg 1 0Z RX_SR_DATA[52] $end
$var reg 1 0[ RX_SR_DATA[51] $end
$var reg 1 0\ RX_SR_DATA[50] $end
$var reg 1 0] RX_SR_DATA[49] $end
$var reg 1 0^ RX_SR_DATA[48] $end
$var reg 1 0_ RX_SR_DATA[47] $end
$var reg 1 0` RX_SR_DATA[46] $end
$var reg 1 0a RX_SR_DATA[45] $end
$var reg 1 0b RX_SR_DATA[44] $end
$var reg 1 0c RX_SR_DATA[43] $end
$var reg 1 0d RX_SR_DATA[42] $end
$var reg 1 0e RX_SR_DATA[41] $end
$var reg 1 0f RX_SR_DATA[40] $end
$var reg 1 0g RX_SR_DATA[39] $end
$var reg 1 0h RX_SR_DATA[38] $end
$var reg 1 0i RX_SR_DATA[37] $end
$var reg 1 0j RX_SR_DATA[36] $end
$var reg 1 0k RX_SR_DATA[35] $end
$var reg 1 0l RX_SR_DATA[34] $end
$var reg 1 0m RX_SR_DATA[33] $end
$var reg 1 0n RX_SR_DATA[32] $end
$var reg 1 0o RX_SR_DATA[31] $end
$var reg 1 0p RX_SR_DATA[30] $end
$var reg 1 0q RX_SR_DATA[29] $end
$var reg 1 0r RX_SR_DATA[28] $end
$var reg 1 0s RX_SR_DATA[27] $end
$var reg 1 0t RX_SR_DATA[26] $end
$var reg 1 0u RX_SR_DATA[25] $end
$var reg 1 0v RX_SR_DATA[24] $end
$var reg 1 0w RX_SR_DATA[23] $end
$var reg 1 0x RX_SR_DATA[22] $end
$var reg 1 0y RX_SR_DATA[21] $end
$var reg 1 0z RX_SR_DATA[20] $end
$var reg 1 0{ RX_SR_DATA[19] $end
$var reg 1 0| RX_SR_DATA[18] $end
$var reg 1 0} RX_SR_DATA[17] $end
$var reg 1 0~ RX_SR_DATA[16] $end
$var reg 1 1! RX_SR_DATA[15] $end
$var reg 1 1" RX_SR_DATA[14] $end
$var reg 1 1# RX_SR_DATA[13] $end
$var reg 1 1$ RX_SR_DATA[12] $end
$var reg 1 1% RX_SR_DATA[11] $end
$var reg 1 1& RX_SR_DATA[10] $end
$var reg 1 1' RX_SR_DATA[9] $end
$var reg 1 1( RX_SR_DATA[8] $end
$var reg 1 1) RX_SR_DATA[7] $end
$var reg 1 1* RX_SR_DATA[6] $end
$var reg 1 1+ RX_SR_DATA[5] $end
$var reg 1 1, RX_SR_DATA[4] $end
$var reg 1 1- RX_SR_DATA[3] $end
$var reg 1 1. RX_SR_DATA[2] $end
$var reg 1 1/ RX_SR_DATA[1] $end
$var reg 1 10 RX_SR_DATA[0] $end
$var reg 1 11 RX_SR_EOP[4] $end
$var reg 1 12 RX_SR_EOP[3] $end
$var reg 1 13 RX_SR_EOP[2] $end
$var reg 1 14 RX_SR_EOP[1] $end
$var reg 1 15 RX_SR_EOP[0] $end
$var reg 1 16 RX_SR_END_OFFSET[19] $end
$var reg 1 17 RX_SR_END_OFFSET[18] $end
$var reg 1 18 RX_SR_END_OFFSET[17] $end
$var reg 1 19 RX_SR_END_OFFSET[16] $end
$var reg 1 1: RX_SR_END_OFFSET[15] $end
$var reg 1 1; RX_SR_END_OFFSET[14] $end
$var reg 1 1< RX_SR_END_OFFSET[13] $end
$var reg 1 1= RX_SR_END_OFFSET[12] $end
$var reg 1 1> RX_SR_END_OFFSET[11] $end
$var reg 1 1? RX_SR_END_OFFSET[10] $end
$var reg 1 1@ RX_SR_END_OFFSET[9] $end
$var reg 1 1A RX_SR_END_OFFSET[8] $end
$var reg 1 1B RX_SR_END_OFFSET[7] $end
$var reg 1 1C RX_SR_END_OFFSET[6] $end
$var reg 1 1D RX_SR_END_OFFSET[5] $end
$var reg 1 1E RX_SR_END_OFFSET[4] $end
$var reg 1 1F RX_SR_END_OFFSET[3] $end
$var reg 1 1G RX_SR_END_OFFSET[2] $end
$var reg 1 1H RX_SR_END_OFFSET[1] $end
$var reg 1 1I RX_SR_END_OFFSET[0] $end
$var reg 1 1J RX_SR_SOP[4] $end
$var reg 1 1K RX_SR_SOP[3] $end
$var reg 1 1L RX_SR_SOP[2] $end
$var reg 1 1M RX_SR_SOP[1] $end
$var reg 1 1N RX_SR_SOP[0] $end
$var reg 1 1O RX_SR_VALID[4] $end
$var reg 1 1P RX_SR_VALID[3] $end
$var reg 1 1Q RX_SR_VALID[2] $end
$var reg 1 1R RX_SR_VALID[1] $end
$var reg 1 1S RX_SR_VALID[0] $end
$var reg 1 1T wStartFlags[3] $end
$var reg 1 1U wStartFlags[2] $end
$var reg 1 1V wStartFlags[1] $end
$var reg 1 1W wStartFlags[0] $end
$var reg 1 1X wEndFlag $end
$var reg 1 1Y rValid $end
$var reg 1 1Z wRxSrSop[2] $end
$var reg 1 1[ wRxSrSop[1] $end
$var reg 1 1\ wRxSrSop[0] $end
$upscope $end
$upscope $end
$scope module tx_engine_classic_inst $end
$scope module txr_engine_inst $end
$scope module txr_formatter_inst $end
$scope module input_inst $end
$scope module pipeline_inst $end
$var reg 1 1] WR_DATA_READY $end
$var reg 1 1^ rValid[1] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module riffa_inst $end
$scope module channels[0].channel $end
$scope module channel $end
$scope module rxPort $end
$scope module mainFifoPacker $end
$var reg 1 1_ rPackedFlush $end
$var reg 1 1` rPackedCount[2] $end
$var reg 1 1a rPackedCount[1] $end
$var reg 1 1b rPackedCount[0] $end
$var reg 1 1c rDataMaskedEn[2] $end
$var reg 1 1d rDataMaskedEn[1] $end
$var reg 1 1e rDataMaskedEn[0] $end
$var reg 1 1f PACKED_WEN $end
$upscope $end
$scope module sgRxFifoPacker $end
$var reg 1 1g rPackedFlush $end
$var reg 1 1h rPackedCount[2] $end
$var reg 1 1i rPackedCount[1] $end
$var reg 1 1j rPackedCount[0] $end
$var reg 1 1k rDataMaskedEn[2] $end
$var reg 1 1l rDataMaskedEn[1] $end
$var reg 1 1m rDataMaskedEn[0] $end
$var reg 1 1n PACKED_WEN $end
$upscope $end
$scope module sgTxFifoPacker $end
$var reg 1 1o PACKED_WEN $end
$var reg 1 1p rPackedFlush $end
$var reg 1 1q rPackedCount[2] $end
$var reg 1 1r rPackedCount[1] $end
$var reg 1 1s rPackedCount[0] $end
$var reg 1 1t DATA_IN_EN[2] $end
$var reg 1 1u DATA_IN_EN[1] $end
$var reg 1 1v DATA_IN_EN[0] $end
$var reg 1 1w rDataMaskedEn[2] $end
$var reg 1 1x rDataMaskedEn[1] $end
$var reg 1 1y rDataMaskedEn[0] $end
$upscope $end
$scope module reader $end
$var reg 1 1z rMainState[5] $end
$var reg 1 1{ rMainState[4] $end
$var reg 1 1| rMainState[3] $end
$var reg 1 1} rMainState[2] $end
$var reg 1 1~ rMainState[1] $end
$var reg 1 2! rMainState[0] $end
$var reg 1 2" rOffLast[0] $end
$var reg 1 2# rRxState[7] $end
$var reg 1 2$ rRxState[6] $end
$var reg 1 2% rRxState[5] $end
$var reg 1 2& rRxState[4] $end
$var reg 1 2' rRxState[3] $end
$var reg 1 2( rRxState[2] $end
$var reg 1 2) rRxState[1] $end
$var reg 1 2* rRxState[0] $end
$var reg 1 2+ rFlushed[3] $end
$var reg 1 2, rFlushed[2] $end
$var reg 1 2- rFlushed[1] $end
$var reg 1 2. rFlushed[0] $end
$var reg 1 2/ rLastDoneRead $end
$var reg 1 20 TXN_DATA_FLUSH $end
$upscope $end
$scope module requesterMux $end
$var reg 1 21 rState[1] $end
$var reg 1 22 rState[0] $end
$var reg 1 23 SG_TX_REQ $end
$var reg 1 24 SG_RX_REQ $end
$var reg 1 25 MAIN_REQ $end
$var reg 1 26 rLen[9] $end
$var reg 1 27 rLen[8] $end
$var reg 1 28 rLen[7] $end
$var reg 1 29 rLen[6] $end
$var reg 1 2: rLen[5] $end
$var reg 1 2; rLen[4] $end
$var reg 1 2< rLen[3] $end
$var reg 1 2= rLen[2] $end
$var reg 1 2> rLen[1] $end
$var reg 1 2? rLen[0] $end
$var reg 1 2@ rAddr[63] $end
$var reg 1 2A rAddr[62] $end
$var reg 1 2B rAddr[61] $end
$var reg 1 2C rAddr[60] $end
$var reg 1 2D rAddr[59] $end
$var reg 1 2E rAddr[58] $end
$var reg 1 2F rAddr[57] $end
$var reg 1 2G rAddr[56] $end
$var reg 1 2H rAddr[55] $end
$var reg 1 2I rAddr[54] $end
$var reg 1 2J rAddr[53] $end
$var reg 1 2K rAddr[52] $end
$var reg 1 2L rAddr[51] $end
$var reg 1 2M rAddr[50] $end
$var reg 1 2N rAddr[49] $end
$var reg 1 2O rAddr[48] $end
$var reg 1 2P rAddr[47] $end
$var reg 1 2Q rAddr[46] $end
$var reg 1 2R rAddr[45] $end
$var reg 1 2S rAddr[44] $end
$var reg 1 2T rAddr[43] $end
$var reg 1 2U rAddr[42] $end
$var reg 1 2V rAddr[41] $end
$var reg 1 2W rAddr[40] $end
$var reg 1 2X rAddr[39] $end
$var reg 1 2Y rAddr[38] $end
$var reg 1 2Z rAddr[37] $end
$var reg 1 2[ rAddr[36] $end
$var reg 1 2\ rAddr[35] $end
$var reg 1 2] rAddr[34] $end
$var reg 1 2^ rAddr[33] $end
$var reg 1 2_ rAddr[32] $end
$var reg 1 2` rAddr[31] $end
$var reg 1 2a rAddr[30] $end
$var reg 1 2b rAddr[29] $end
$var reg 1 2c rAddr[28] $end
$var reg 1 2d rAddr[27] $end
$var reg 1 2e rAddr[26] $end
$var reg 1 2f rAddr[25] $end
$var reg 1 2g rAddr[24] $end
$var reg 1 2h rAddr[23] $end
$var reg 1 2i rAddr[22] $end
$var reg 1 2j rAddr[21] $end
$var reg 1 2k rAddr[20] $end
$var reg 1 2l rAddr[19] $end
$var reg 1 2m rAddr[18] $end
$var reg 1 2n rAddr[17] $end
$var reg 1 2o rAddr[16] $end
$var reg 1 2p rAddr[15] $end
$var reg 1 2q rAddr[14] $end
$var reg 1 2r rAddr[13] $end
$var reg 1 2s rAddr[12] $end
$var reg 1 2t rAddr[11] $end
$var reg 1 2u rAddr[10] $end
$var reg 1 2v rAddr[9] $end
$var reg 1 2w rAddr[8] $end
$var reg 1 2x rAddr[7] $end
$var reg 1 2y rAddr[6] $end
$var reg 1 2z rAddr[5] $end
$var reg 1 2{ rAddr[4] $end
$var reg 1 2| rAddr[3] $end
$var reg 1 2} rAddr[2] $end
$var reg 1 2~ rAddr[1] $end
$var reg 1 3! rAddr[0] $end
$var reg 1 3" rRxReqAck $end
$var reg 1 3# rSgRxAck $end
$var reg 1 3$ rMainAck $end
$upscope $end
$scope module sgListReader $end
$var reg 1 3% EMPTY $end
$var reg 1 3& ADDR[63] $end
$var reg 1 3' ADDR[62] $end
$var reg 1 3( ADDR[61] $end
$var reg 1 3) ADDR[60] $end
$var reg 1 3* ADDR[59] $end
$var reg 1 3+ ADDR[58] $end
$var reg 1 3, ADDR[57] $end
$var reg 1 3- ADDR[56] $end
$var reg 1 3. ADDR[55] $end
$var reg 1 3/ ADDR[54] $end
$var reg 1 30 ADDR[53] $end
$var reg 1 31 ADDR[52] $end
$var reg 1 32 ADDR[51] $end
$var reg 1 33 ADDR[50] $end
$var reg 1 34 ADDR[49] $end
$var reg 1 35 ADDR[48] $end
$var reg 1 36 ADDR[47] $end
$var reg 1 37 ADDR[46] $end
$var reg 1 38 ADDR[45] $end
$var reg 1 39 ADDR[44] $end
$var reg 1 3: ADDR[43] $end
$var reg 1 3; ADDR[42] $end
$var reg 1 3< ADDR[41] $end
$var reg 1 3= ADDR[40] $end
$var reg 1 3> ADDR[39] $end
$var reg 1 3? ADDR[38] $end
$var reg 1 3@ ADDR[37] $end
$var reg 1 3A ADDR[36] $end
$var reg 1 3B ADDR[35] $end
$var reg 1 3C ADDR[34] $end
$var reg 1 3D ADDR[33] $end
$var reg 1 3E ADDR[32] $end
$var reg 1 3F ADDR[31] $end
$var reg 1 3G ADDR[30] $end
$var reg 1 3H ADDR[29] $end
$var reg 1 3I ADDR[28] $end
$var reg 1 3J ADDR[27] $end
$var reg 1 3K ADDR[26] $end
$var reg 1 3L ADDR[25] $end
$var reg 1 3M ADDR[24] $end
$var reg 1 3N ADDR[23] $end
$var reg 1 3O ADDR[22] $end
$var reg 1 3P ADDR[21] $end
$var reg 1 3Q ADDR[20] $end
$var reg 1 3R ADDR[19] $end
$var reg 1 3S ADDR[18] $end
$var reg 1 3T ADDR[17] $end
$var reg 1 3U ADDR[16] $end
$var reg 1 3V ADDR[15] $end
$var reg 1 3W ADDR[14] $end
$var reg 1 3X ADDR[13] $end
$var reg 1 3Y ADDR[12] $end
$var reg 1 3Z ADDR[11] $end
$var reg 1 3[ ADDR[10] $end
$var reg 1 3\ ADDR[9] $end
$var reg 1 3] ADDR[8] $end
$var reg 1 3^ ADDR[7] $end
$var reg 1 3_ ADDR[6] $end
$var reg 1 3` ADDR[5] $end
$var reg 1 3a ADDR[4] $end
$var reg 1 3b ADDR[3] $end
$var reg 1 3c ADDR[2] $end
$var reg 1 3d ADDR[1] $end
$var reg 1 3e ADDR[0] $end
$var reg 1 3f BUF_DATA[127] $end
$var reg 1 3g BUF_DATA[126] $end
$var reg 1 3h BUF_DATA[125] $end
$var reg 1 3i BUF_DATA[124] $end
$var reg 1 3j BUF_DATA[123] $end
$var reg 1 3k BUF_DATA[122] $end
$var reg 1 3l BUF_DATA[121] $end
$var reg 1 3m BUF_DATA[120] $end
$var reg 1 3n BUF_DATA[119] $end
$var reg 1 3o BUF_DATA[118] $end
$var reg 1 3p BUF_DATA[117] $end
$var reg 1 3q BUF_DATA[116] $end
$var reg 1 3r BUF_DATA[115] $end
$var reg 1 3s BUF_DATA[114] $end
$var reg 1 3t BUF_DATA[113] $end
$var reg 1 3u BUF_DATA[112] $end
$var reg 1 3v BUF_DATA[111] $end
$var reg 1 3w BUF_DATA[110] $end
$var reg 1 3x BUF_DATA[109] $end
$var reg 1 3y BUF_DATA[108] $end
$var reg 1 3z BUF_DATA[107] $end
$var reg 1 3{ BUF_DATA[106] $end
$var reg 1 3| BUF_DATA[105] $end
$var reg 1 3} BUF_DATA[104] $end
$var reg 1 3~ BUF_DATA[103] $end
$var reg 1 4! BUF_DATA[102] $end
$var reg 1 4" BUF_DATA[101] $end
$var reg 1 4# BUF_DATA[100] $end
$var reg 1 4$ BUF_DATA[99] $end
$var reg 1 4% BUF_DATA[98] $end
$var reg 1 4& BUF_DATA[97] $end
$var reg 1 4' BUF_DATA[96] $end
$var reg 1 4( BUF_DATA[95] $end
$var reg 1 4) BUF_DATA[94] $end
$var reg 1 4* BUF_DATA[93] $end
$var reg 1 4+ BUF_DATA[92] $end
$var reg 1 4, BUF_DATA[91] $end
$var reg 1 4- BUF_DATA[90] $end
$var reg 1 4. BUF_DATA[89] $end
$var reg 1 4/ BUF_DATA[88] $end
$var reg 1 40 BUF_DATA[87] $end
$var reg 1 41 BUF_DATA[86] $end
$var reg 1 42 BUF_DATA[85] $end
$var reg 1 43 BUF_DATA[84] $end
$var reg 1 44 BUF_DATA[83] $end
$var reg 1 45 BUF_DATA[82] $end
$var reg 1 46 BUF_DATA[81] $end
$var reg 1 47 BUF_DATA[80] $end
$var reg 1 48 BUF_DATA[79] $end
$var reg 1 49 BUF_DATA[78] $end
$var reg 1 4: BUF_DATA[77] $end
$var reg 1 4; BUF_DATA[76] $end
$var reg 1 4< BUF_DATA[75] $end
$var reg 1 4= BUF_DATA[74] $end
$var reg 1 4> BUF_DATA[73] $end
$var reg 1 4? BUF_DATA[72] $end
$var reg 1 4@ BUF_DATA[71] $end
$var reg 1 4A BUF_DATA[70] $end
$var reg 1 4B BUF_DATA[69] $end
$var reg 1 4C BUF_DATA[68] $end
$var reg 1 4D BUF_DATA[67] $end
$var reg 1 4E BUF_DATA[66] $end
$var reg 1 4F BUF_DATA[65] $end
$var reg 1 4G BUF_DATA[64] $end
$var reg 1 4H BUF_DATA[63] $end
$var reg 1 4I BUF_DATA[62] $end
$var reg 1 4J BUF_DATA[61] $end
$var reg 1 4K BUF_DATA[60] $end
$var reg 1 4L BUF_DATA[59] $end
$var reg 1 4M BUF_DATA[58] $end
$var reg 1 4N BUF_DATA[57] $end
$var reg 1 4O BUF_DATA[56] $end
$var reg 1 4P BUF_DATA[55] $end
$var reg 1 4Q BUF_DATA[54] $end
$var reg 1 4R BUF_DATA[53] $end
$var reg 1 4S BUF_DATA[52] $end
$var reg 1 4T BUF_DATA[51] $end
$var reg 1 4U BUF_DATA[50] $end
$var reg 1 4V BUF_DATA[49] $end
$var reg 1 4W BUF_DATA[48] $end
$var reg 1 4X BUF_DATA[47] $end
$var reg 1 4Y BUF_DATA[46] $end
$var reg 1 4Z BUF_DATA[45] $end
$var reg 1 4[ BUF_DATA[44] $end
$var reg 1 4\ BUF_DATA[43] $end
$var reg 1 4] BUF_DATA[42] $end
$var reg 1 4^ BUF_DATA[41] $end
$var reg 1 4_ BUF_DATA[40] $end
$var reg 1 4` BUF_DATA[39] $end
$var reg 1 4a BUF_DATA[38] $end
$var reg 1 4b BUF_DATA[37] $end
$var reg 1 4c BUF_DATA[36] $end
$var reg 1 4d BUF_DATA[35] $end
$var reg 1 4e BUF_DATA[34] $end
$var reg 1 4f BUF_DATA[33] $end
$var reg 1 4g BUF_DATA[32] $end
$var reg 1 4h BUF_DATA[31] $end
$var reg 1 4i BUF_DATA[30] $end
$var reg 1 4j BUF_DATA[29] $end
$var reg 1 4k BUF_DATA[28] $end
$var reg 1 4l BUF_DATA[27] $end
$var reg 1 4m BUF_DATA[26] $end
$var reg 1 4n BUF_DATA[25] $end
$var reg 1 4o BUF_DATA[24] $end
$var reg 1 4p BUF_DATA[23] $end
$var reg 1 4q BUF_DATA[22] $end
$var reg 1 4r BUF_DATA[21] $end
$var reg 1 4s BUF_DATA[20] $end
$var reg 1 4t BUF_DATA[19] $end
$var reg 1 4u BUF_DATA[18] $end
$var reg 1 4v BUF_DATA[17] $end
$var reg 1 4w BUF_DATA[16] $end
$var reg 1 4x BUF_DATA[15] $end
$var reg 1 4y BUF_DATA[14] $end
$var reg 1 4z BUF_DATA[13] $end
$var reg 1 4{ BUF_DATA[12] $end
$var reg 1 4| BUF_DATA[11] $end
$var reg 1 4} BUF_DATA[10] $end
$var reg 1 4~ BUF_DATA[9] $end
$var reg 1 5! BUF_DATA[8] $end
$var reg 1 5" BUF_DATA[7] $end
$var reg 1 5# BUF_DATA[6] $end
$var reg 1 5$ BUF_DATA[5] $end
$var reg 1 5% BUF_DATA[4] $end
$var reg 1 5& BUF_DATA[3] $end
$var reg 1 5' BUF_DATA[2] $end
$var reg 1 5( BUF_DATA[1] $end
$var reg 1 5) BUF_DATA[0] $end
$var reg 1 5* BUF_DATA_EMPTY $end
$var reg 1 5+ BUF_DATA_REN $end
$var reg 1 5, LEN[31] $end
$var reg 1 5- LEN[30] $end
$var reg 1 5. LEN[29] $end
$var reg 1 5/ LEN[28] $end
$var reg 1 50 LEN[27] $end
$var reg 1 51 LEN[26] $end
$var reg 1 52 LEN[25] $end
$var reg 1 53 LEN[24] $end
$var reg 1 54 LEN[23] $end
$var reg 1 55 LEN[22] $end
$var reg 1 56 LEN[21] $end
$var reg 1 57 LEN[20] $end
$var reg 1 58 LEN[19] $end
$var reg 1 59 LEN[18] $end
$var reg 1 5: LEN[17] $end
$var reg 1 5; LEN[16] $end
$var reg 1 5< LEN[15] $end
$var reg 1 5= LEN[14] $end
$var reg 1 5> LEN[13] $end
$var reg 1 5? LEN[12] $end
$var reg 1 5@ LEN[11] $end
$var reg 1 5A LEN[10] $end
$var reg 1 5B LEN[9] $end
$var reg 1 5C LEN[8] $end
$var reg 1 5D LEN[7] $end
$var reg 1 5E LEN[6] $end
$var reg 1 5F LEN[5] $end
$var reg 1 5G LEN[4] $end
$var reg 1 5H LEN[3] $end
$var reg 1 5I LEN[2] $end
$var reg 1 5J LEN[1] $end
$var reg 1 5K LEN[0] $end
$var reg 1 5L REN $end
$var reg 1 5M RST $end
$var reg 1 5N VALID $end
$upscope $end
$scope module sgRxReq $end
$var reg 1 5O BUF_ADDR_HI_VALID $end
$var reg 1 5P BUF_ADDR_LO_VALID $end
$var reg 1 5Q BUF_DATA[31] $end
$var reg 1 5R BUF_DATA[30] $end
$var reg 1 5S BUF_DATA[29] $end
$var reg 1 5T BUF_DATA[28] $end
$var reg 1 5U BUF_DATA[27] $end
$var reg 1 5V BUF_DATA[26] $end
$var reg 1 5W BUF_DATA[25] $end
$var reg 1 5X BUF_DATA[24] $end
$var reg 1 5Y BUF_DATA[23] $end
$var reg 1 5Z BUF_DATA[22] $end
$var reg 1 5[ BUF_DATA[21] $end
$var reg 1 5\ BUF_DATA[20] $end
$var reg 1 5] BUF_DATA[19] $end
$var reg 1 5^ BUF_DATA[18] $end
$var reg 1 5_ BUF_DATA[17] $end
$var reg 1 5` BUF_DATA[16] $end
$var reg 1 5a BUF_DATA[15] $end
$var reg 1 5b BUF_DATA[14] $end
$var reg 1 5c BUF_DATA[13] $end
$var reg 1 5d BUF_DATA[12] $end
$var reg 1 5e BUF_DATA[11] $end
$var reg 1 5f BUF_DATA[10] $end
$var reg 1 5g BUF_DATA[9] $end
$var reg 1 5h BUF_DATA[8] $end
$var reg 1 5i BUF_DATA[7] $end
$var reg 1 5j BUF_DATA[6] $end
$var reg 1 5k BUF_DATA[5] $end
$var reg 1 5l BUF_DATA[4] $end
$var reg 1 5m BUF_DATA[3] $end
$var reg 1 5n BUF_DATA[2] $end
$var reg 1 5o BUF_DATA[1] $end
$var reg 1 5p BUF_DATA[0] $end
$var reg 1 5q BUF_LEN_VALID $end
$var reg 1 5r BUF_RECVD $end
$var reg 1 5s CONFIG_MAX_READ_REQUEST_SIZE[2] $end
$var reg 1 5t CONFIG_MAX_READ_REQUEST_SIZE[1] $end
$var reg 1 5u CONFIG_MAX_READ_REQUEST_SIZE[0] $end
$var reg 1 5v FIFO_COUNT[10] $end
$var reg 1 5w FIFO_COUNT[9] $end
$var reg 1 5x FIFO_COUNT[8] $end
$var reg 1 5y FIFO_COUNT[7] $end
$var reg 1 5z FIFO_COUNT[6] $end
$var reg 1 5{ FIFO_COUNT[5] $end
$var reg 1 5| FIFO_COUNT[4] $end
$var reg 1 5} FIFO_COUNT[3] $end
$var reg 1 5~ FIFO_COUNT[2] $end
$var reg 1 6! FIFO_COUNT[1] $end
$var reg 1 6" FIFO_COUNT[0] $end
$var reg 1 6# FIFO_FLUSH $end
$var reg 1 6$ FIFO_FLUSHED $end
$var reg 1 6% FIFO_RST $end
$var reg 1 6& RX_ADDR[63] $end
$var reg 1 6' RX_ADDR[62] $end
$var reg 1 6( RX_ADDR[61] $end
$var reg 1 6) RX_ADDR[60] $end
$var reg 1 6* RX_ADDR[59] $end
$var reg 1 6+ RX_ADDR[58] $end
$var reg 1 6, RX_ADDR[57] $end
$var reg 1 6- RX_ADDR[56] $end
$var reg 1 6. RX_ADDR[55] $end
$var reg 1 6/ RX_ADDR[54] $end
$var reg 1 60 RX_ADDR[53] $end
$var reg 1 61 RX_ADDR[52] $end
$var reg 1 62 RX_ADDR[51] $end
$var reg 1 63 RX_ADDR[50] $end
$var reg 1 64 RX_ADDR[49] $end
$var reg 1 65 RX_ADDR[48] $end
$var reg 1 66 RX_ADDR[47] $end
$var reg 1 67 RX_ADDR[46] $end
$var reg 1 68 RX_ADDR[45] $end
$var reg 1 69 RX_ADDR[44] $end
$var reg 1 6: RX_ADDR[43] $end
$var reg 1 6; RX_ADDR[42] $end
$var reg 1 6< RX_ADDR[41] $end
$var reg 1 6= RX_ADDR[40] $end
$var reg 1 6> RX_ADDR[39] $end
$var reg 1 6? RX_ADDR[38] $end
$var reg 1 6@ RX_ADDR[37] $end
$var reg 1 6A RX_ADDR[36] $end
$var reg 1 6B RX_ADDR[35] $end
$var reg 1 6C RX_ADDR[34] $end
$var reg 1 6D RX_ADDR[33] $end
$var reg 1 6E RX_ADDR[32] $end
$var reg 1 6F RX_ADDR[31] $end
$var reg 1 6G RX_ADDR[30] $end
$var reg 1 6H RX_ADDR[29] $end
$var reg 1 6I RX_ADDR[28] $end
$var reg 1 6J RX_ADDR[27] $end
$var reg 1 6K RX_ADDR[26] $end
$var reg 1 6L RX_ADDR[25] $end
$var reg 1 6M RX_ADDR[24] $end
$var reg 1 6N RX_ADDR[23] $end
$var reg 1 6O RX_ADDR[22] $end
$var reg 1 6P RX_ADDR[21] $end
$var reg 1 6Q RX_ADDR[20] $end
$var reg 1 6R RX_ADDR[19] $end
$var reg 1 6S RX_ADDR[18] $end
$var reg 1 6T RX_ADDR[17] $end
$var reg 1 6U RX_ADDR[16] $end
$var reg 1 6V RX_ADDR[15] $end
$var reg 1 6W RX_ADDR[14] $end
$var reg 1 6X RX_ADDR[13] $end
$var reg 1 6Y RX_ADDR[12] $end
$var reg 1 6Z RX_ADDR[11] $end
$var reg 1 6[ RX_ADDR[10] $end
$var reg 1 6\ RX_ADDR[9] $end
$var reg 1 6] RX_ADDR[8] $end
$var reg 1 6^ RX_ADDR[7] $end
$var reg 1 6_ RX_ADDR[6] $end
$var reg 1 6` RX_ADDR[5] $end
$var reg 1 6a RX_ADDR[4] $end
$var reg 1 6b RX_ADDR[3] $end
$var reg 1 6c RX_ADDR[2] $end
$var reg 1 6d RX_ADDR[1] $end
$var reg 1 6e RX_ADDR[0] $end
$var reg 1 6f RX_DONE $end
$var reg 1 6g RX_LEN[9] $end
$var reg 1 6h RX_LEN[8] $end
$var reg 1 6i RX_LEN[7] $end
$var reg 1 6j RX_LEN[6] $end
$var reg 1 6k RX_LEN[5] $end
$var reg 1 6l RX_LEN[4] $end
$var reg 1 6m RX_LEN[3] $end
$var reg 1 6n RX_LEN[2] $end
$var reg 1 6o RX_LEN[1] $end
$var reg 1 6p RX_LEN[0] $end
$var reg 1 6q RX_REQ $end
$var reg 1 6r RX_REQ_ACK $end
$var reg 1 6s USER_RST $end
$var reg 1 6t rState[7] $end
$var reg 1 6u rState[6] $end
$var reg 1 6v rState[5] $end
$var reg 1 6w rState[4] $end
$var reg 1 6x rState[3] $end
$var reg 1 6y rState[2] $end
$var reg 1 6z rState[1] $end
$var reg 1 6{ rState[0] $end
$upscope $end
$scope module sgTxReq $end
$var reg 1 6| CONFIG_MAX_READ_REQUEST_SIZE[2] $end
$var reg 1 6} CONFIG_MAX_READ_REQUEST_SIZE[1] $end
$var reg 1 6~ CONFIG_MAX_READ_REQUEST_SIZE[0] $end
$var reg 1 7! FIFO_COUNT[10] $end
$var reg 1 7" FIFO_COUNT[9] $end
$var reg 1 7# FIFO_COUNT[8] $end
$var reg 1 7$ FIFO_COUNT[7] $end
$var reg 1 7% FIFO_COUNT[6] $end
$var reg 1 7& FIFO_COUNT[5] $end
$var reg 1 7' FIFO_COUNT[4] $end
$var reg 1 7( FIFO_COUNT[3] $end
$var reg 1 7) FIFO_COUNT[2] $end
$var reg 1 7* FIFO_COUNT[1] $end
$var reg 1 7+ FIFO_COUNT[0] $end
$var reg 1 7, FIFO_FLUSH $end
$var reg 1 7- FIFO_FLUSHED $end
$var reg 1 7. FIFO_RST $end
$var reg 1 7/ RST $end
$var reg 1 70 RX_ADDR[63] $end
$var reg 1 71 RX_ADDR[62] $end
$var reg 1 72 RX_ADDR[61] $end
$var reg 1 73 RX_ADDR[60] $end
$var reg 1 74 RX_ADDR[59] $end
$var reg 1 75 RX_ADDR[58] $end
$var reg 1 76 RX_ADDR[57] $end
$var reg 1 77 RX_ADDR[56] $end
$var reg 1 78 RX_ADDR[55] $end
$var reg 1 79 RX_ADDR[54] $end
$var reg 1 7: RX_ADDR[53] $end
$var reg 1 7; RX_ADDR[52] $end
$var reg 1 7< RX_ADDR[51] $end
$var reg 1 7= RX_ADDR[50] $end
$var reg 1 7> RX_ADDR[49] $end
$var reg 1 7? RX_ADDR[48] $end
$var reg 1 7@ RX_ADDR[47] $end
$var reg 1 7A RX_ADDR[46] $end
$var reg 1 7B RX_ADDR[45] $end
$var reg 1 7C RX_ADDR[44] $end
$var reg 1 7D RX_ADDR[43] $end
$var reg 1 7E RX_ADDR[42] $end
$var reg 1 7F RX_ADDR[41] $end
$var reg 1 7G RX_ADDR[40] $end
$var reg 1 7H RX_ADDR[39] $end
$var reg 1 7I RX_ADDR[38] $end
$var reg 1 7J RX_ADDR[37] $end
$var reg 1 7K RX_ADDR[36] $end
$var reg 1 7L RX_ADDR[35] $end
$var reg 1 7M RX_ADDR[34] $end
$var reg 1 7N RX_ADDR[33] $end
$var reg 1 7O RX_ADDR[32] $end
$var reg 1 7P RX_ADDR[31] $end
$var reg 1 7Q RX_ADDR[30] $end
$var reg 1 7R RX_ADDR[29] $end
$var reg 1 7S RX_ADDR[28] $end
$var reg 1 7T RX_ADDR[27] $end
$var reg 1 7U RX_ADDR[26] $end
$var reg 1 7V RX_ADDR[25] $end
$var reg 1 7W RX_ADDR[24] $end
$var reg 1 7X RX_ADDR[23] $end
$var reg 1 7Y RX_ADDR[22] $end
$var reg 1 7Z RX_ADDR[21] $end
$var reg 1 7[ RX_ADDR[20] $end
$var reg 1 7\ RX_ADDR[19] $end
$var reg 1 7] RX_ADDR[18] $end
$var reg 1 7^ RX_ADDR[17] $end
$var reg 1 7_ RX_ADDR[16] $end
$var reg 1 7` RX_ADDR[15] $end
$var reg 1 7a RX_ADDR[14] $end
$var reg 1 7b RX_ADDR[13] $end
$var reg 1 7c RX_ADDR[12] $end
$var reg 1 7d RX_ADDR[11] $end
$var reg 1 7e RX_ADDR[10] $end
$var reg 1 7f RX_ADDR[9] $end
$var reg 1 7g RX_ADDR[8] $end
$var reg 1 7h RX_ADDR[7] $end
$var reg 1 7i RX_ADDR[6] $end
$var reg 1 7j RX_ADDR[5] $end
$var reg 1 7k RX_ADDR[4] $end
$var reg 1 7l RX_ADDR[3] $end
$var reg 1 7m RX_ADDR[2] $end
$var reg 1 7n RX_ADDR[1] $end
$var reg 1 7o RX_ADDR[0] $end
$var reg 1 7p RX_DONE $end
$var reg 1 7q RX_LEN[9] $end
$var reg 1 7r RX_LEN[8] $end
$var reg 1 7s RX_LEN[7] $end
$var reg 1 7t RX_LEN[6] $end
$var reg 1 7u RX_LEN[5] $end
$var reg 1 7v RX_LEN[4] $end
$var reg 1 7w RX_LEN[3] $end
$var reg 1 7x RX_LEN[2] $end
$var reg 1 7y RX_LEN[1] $end
$var reg 1 7z RX_LEN[0] $end
$var reg 1 7{ RX_REQ $end
$var reg 1 7| RX_REQ_ACK $end
$var reg 1 7} USER_RST $end
$var reg 1 7~ BUF_RECVD $end
$var reg 1 8! BUF_LEN_VALID $end
$var reg 1 8" BUF_DATA[31] $end
$var reg 1 8# BUF_DATA[30] $end
$var reg 1 8$ BUF_DATA[29] $end
$var reg 1 8% BUF_DATA[28] $end
$var reg 1 8& BUF_DATA[27] $end
$var reg 1 8' BUF_DATA[26] $end
$var reg 1 8( BUF_DATA[25] $end
$var reg 1 8) BUF_DATA[24] $end
$var reg 1 8* BUF_DATA[23] $end
$var reg 1 8+ BUF_DATA[22] $end
$var reg 1 8, BUF_DATA[21] $end
$var reg 1 8- BUF_DATA[20] $end
$var reg 1 8. BUF_DATA[19] $end
$var reg 1 8/ BUF_DATA[18] $end
$var reg 1 80 BUF_DATA[17] $end
$var reg 1 81 BUF_DATA[16] $end
$var reg 1 82 BUF_DATA[15] $end
$var reg 1 83 BUF_DATA[14] $end
$var reg 1 84 BUF_DATA[13] $end
$var reg 1 85 BUF_DATA[12] $end
$var reg 1 86 BUF_DATA[11] $end
$var reg 1 87 BUF_DATA[10] $end
$var reg 1 88 BUF_DATA[9] $end
$var reg 1 89 BUF_DATA[8] $end
$var reg 1 8: BUF_DATA[7] $end
$var reg 1 8; BUF_DATA[6] $end
$var reg 1 8< BUF_DATA[5] $end
$var reg 1 8= BUF_DATA[4] $end
$var reg 1 8> BUF_DATA[3] $end
$var reg 1 8? BUF_DATA[2] $end
$var reg 1 8@ BUF_DATA[1] $end
$var reg 1 8A BUF_DATA[0] $end
$var reg 1 8B BUF_ADDR_LO_VALID $end
$var reg 1 8C BUF_ADDR_HI_VALID $end
$var reg 1 8D rState[7] $end
$var reg 1 8E rState[6] $end
$var reg 1 8F rState[5] $end
$var reg 1 8G rState[4] $end
$var reg 1 8H rState[3] $end
$var reg 1 8I rState[2] $end
$var reg 1 8J rState[1] $end
$var reg 1 8K rState[0] $end
$upscope $end
$upscope $end
$scope module txPort $end
$var reg 1 8L TX_DATA_REN $end
$scope module sgListReader $end
$var reg 1 8M rCapState $end
$var reg 1 8N rDataValid $end
$var reg 1 8O REN $end
$var reg 1 8P BUF_DATA_EMPTY $end
$var reg 1 8Q BUF_DATA_REN $end
$upscope $end
$scope module buffer $end
$var reg 1 8R WR_EN $end
$var reg 1 8S RD_EN $end
$var reg 1 8T WR_COUNT[9] $end
$var reg 1 8U WR_COUNT[8] $end
$var reg 1 8V WR_COUNT[7] $end
$var reg 1 8W WR_COUNT[6] $end
$var reg 1 8X WR_COUNT[5] $end
$var reg 1 8Y WR_COUNT[4] $end
$var reg 1 8Z WR_COUNT[3] $end
$var reg 1 8[ WR_COUNT[2] $end
$var reg 1 8\ WR_COUNT[1] $end
$var reg 1 8] WR_COUNT[0] $end
$upscope $end
$scope module gate $end
$var reg 1 8^ rChnlTx $end
$var reg 1 8_ \rState.00  $end
$var reg 1 8` \rState.01  $end
$var reg 1 8a \rState.10  $end
$var reg 1 8b \rState.11  $end
$scope module fifo $end
$var reg 1 8c WR_EN $end
$var reg 1 8d RD_EN $end
$var reg 1 8e RD_DATA[128] $end
$var reg 1 8f RD_DATA[127] $end
$var reg 1 8g RD_DATA[126] $end
$var reg 1 8h RD_DATA[125] $end
$var reg 1 8i RD_DATA[124] $end
$var reg 1 8j RD_DATA[123] $end
$var reg 1 8k RD_DATA[122] $end
$var reg 1 8l RD_DATA[121] $end
$var reg 1 8m RD_DATA[120] $end
$var reg 1 8n RD_DATA[119] $end
$var reg 1 8o RD_DATA[118] $end
$var reg 1 8p RD_DATA[117] $end
$var reg 1 8q RD_DATA[116] $end
$var reg 1 8r RD_DATA[115] $end
$var reg 1 8s RD_DATA[114] $end
$var reg 1 8t RD_DATA[113] $end
$var reg 1 8u RD_DATA[112] $end
$var reg 1 8v RD_DATA[111] $end
$var reg 1 8w RD_DATA[110] $end
$var reg 1 8x RD_DATA[109] $end
$var reg 1 8y RD_DATA[108] $end
$var reg 1 8z RD_DATA[107] $end
$var reg 1 8{ RD_DATA[106] $end
$var reg 1 8| RD_DATA[105] $end
$var reg 1 8} RD_DATA[104] $end
$var reg 1 8~ RD_DATA[103] $end
$var reg 1 9! RD_DATA[102] $end
$var reg 1 9" RD_DATA[101] $end
$var reg 1 9# RD_DATA[100] $end
$var reg 1 9$ RD_DATA[99] $end
$var reg 1 9% RD_DATA[98] $end
$var reg 1 9& RD_DATA[97] $end
$var reg 1 9' RD_DATA[96] $end
$var reg 1 9( RD_DATA[95] $end
$var reg 1 9) RD_DATA[94] $end
$var reg 1 9* RD_DATA[93] $end
$var reg 1 9+ RD_DATA[92] $end
$var reg 1 9, RD_DATA[91] $end
$var reg 1 9- RD_DATA[90] $end
$var reg 1 9. RD_DATA[89] $end
$var reg 1 9/ RD_DATA[88] $end
$var reg 1 90 RD_DATA[87] $end
$var reg 1 91 RD_DATA[86] $end
$var reg 1 92 RD_DATA[85] $end
$var reg 1 93 RD_DATA[84] $end
$var reg 1 94 RD_DATA[83] $end
$var reg 1 95 RD_DATA[82] $end
$var reg 1 96 RD_DATA[81] $end
$var reg 1 97 RD_DATA[80] $end
$var reg 1 98 RD_DATA[79] $end
$var reg 1 99 RD_DATA[78] $end
$var reg 1 9: RD_DATA[77] $end
$var reg 1 9; RD_DATA[76] $end
$var reg 1 9< RD_DATA[75] $end
$var reg 1 9= RD_DATA[74] $end
$var reg 1 9> RD_DATA[73] $end
$var reg 1 9? RD_DATA[72] $end
$var reg 1 9@ RD_DATA[71] $end
$var reg 1 9A RD_DATA[70] $end
$var reg 1 9B RD_DATA[69] $end
$var reg 1 9C RD_DATA[68] $end
$var reg 1 9D RD_DATA[67] $end
$var reg 1 9E RD_DATA[66] $end
$var reg 1 9F RD_DATA[65] $end
$var reg 1 9G RD_DATA[64] $end
$var reg 1 9H RD_DATA[63] $end
$var reg 1 9I RD_DATA[62] $end
$var reg 1 9J RD_DATA[61] $end
$var reg 1 9K RD_DATA[60] $end
$var reg 1 9L RD_DATA[59] $end
$var reg 1 9M RD_DATA[58] $end
$var reg 1 9N RD_DATA[57] $end
$var reg 1 9O RD_DATA[56] $end
$var reg 1 9P RD_DATA[55] $end
$var reg 1 9Q RD_DATA[54] $end
$var reg 1 9R RD_DATA[53] $end
$var reg 1 9S RD_DATA[52] $end
$var reg 1 9T RD_DATA[51] $end
$var reg 1 9U RD_DATA[50] $end
$var reg 1 9V RD_DATA[49] $end
$var reg 1 9W RD_DATA[48] $end
$var reg 1 9X RD_DATA[47] $end
$var reg 1 9Y RD_DATA[46] $end
$var reg 1 9Z RD_DATA[45] $end
$var reg 1 9[ RD_DATA[44] $end
$var reg 1 9\ RD_DATA[43] $end
$var reg 1 9] RD_DATA[42] $end
$var reg 1 9^ RD_DATA[41] $end
$var reg 1 9_ RD_DATA[40] $end
$var reg 1 9` RD_DATA[39] $end
$var reg 1 9a RD_DATA[38] $end
$var reg 1 9b RD_DATA[37] $end
$var reg 1 9c RD_DATA[36] $end
$var reg 1 9d RD_DATA[35] $end
$var reg 1 9e RD_DATA[34] $end
$var reg 1 9f RD_DATA[33] $end
$var reg 1 9g RD_DATA[32] $end
$var reg 1 9h RD_DATA[31] $end
$var reg 1 9i RD_DATA[30] $end
$var reg 1 9j RD_DATA[29] $end
$var reg 1 9k RD_DATA[28] $end
$var reg 1 9l RD_DATA[27] $end
$var reg 1 9m RD_DATA[26] $end
$var reg 1 9n RD_DATA[25] $end
$var reg 1 9o RD_DATA[24] $end
$var reg 1 9p RD_DATA[23] $end
$var reg 1 9q RD_DATA[22] $end
$var reg 1 9r RD_DATA[21] $end
$var reg 1 9s RD_DATA[20] $end
$var reg 1 9t RD_DATA[19] $end
$var reg 1 9u RD_DATA[18] $end
$var reg 1 9v RD_DATA[17] $end
$var reg 1 9w RD_DATA[16] $end
$var reg 1 9x RD_DATA[15] $end
$var reg 1 9y RD_DATA[14] $end
$var reg 1 9z RD_DATA[13] $end
$var reg 1 9{ RD_DATA[12] $end
$var reg 1 9| RD_DATA[11] $end
$var reg 1 9} RD_DATA[10] $end
$var reg 1 9~ RD_DATA[9] $end
$var reg 1 :! RD_DATA[8] $end
$var reg 1 :" RD_DATA[7] $end
$var reg 1 :# RD_DATA[6] $end
$var reg 1 :$ RD_DATA[5] $end
$var reg 1 :% RD_DATA[4] $end
$var reg 1 :& RD_DATA[3] $end
$var reg 1 :' RD_DATA[2] $end
$var reg 1 :( RD_DATA[1] $end
$var reg 1 :) RD_DATA[0] $end
$var reg 1 :* WR_FULL $end
$var reg 1 :+ RD_EMPTY $end
$upscope $end
$upscope $end
$scope module monitor $end
$var reg 1 :, rState[5] $end
$var reg 1 :- rState[4] $end
$var reg 1 :. rState[3] $end
$var reg 1 :/ rState[2] $end
$var reg 1 :0 rState[1] $end
$var reg 1 :1 rState[0] $end
$var reg 1 :2 rEvent $end
$var reg 1 :3 rAlmostFull $end
$var reg 1 :4 rDataValid[0] $end
$var reg 1 :5 TX_ERR $end
$var reg 1 :6 ACK $end
$var reg 1 :7 rWordsRecvdAdv[31] $end
$var reg 1 :8 rWordsRecvdAdv[30] $end
$var reg 1 :9 rWordsRecvdAdv[29] $end
$var reg 1 :: rWordsRecvdAdv[28] $end
$var reg 1 :; rWordsRecvdAdv[27] $end
$var reg 1 :< rWordsRecvdAdv[26] $end
$var reg 1 := rWordsRecvdAdv[25] $end
$var reg 1 :> rWordsRecvdAdv[24] $end
$var reg 1 :? rWordsRecvdAdv[23] $end
$var reg 1 :@ rWordsRecvdAdv[22] $end
$var reg 1 :A rWordsRecvdAdv[21] $end
$var reg 1 :B rWordsRecvdAdv[20] $end
$var reg 1 :C rWordsRecvdAdv[19] $end
$var reg 1 :D rWordsRecvdAdv[18] $end
$var reg 1 :E rWordsRecvdAdv[17] $end
$var reg 1 :F rWordsRecvdAdv[16] $end
$var reg 1 :G rWordsRecvdAdv[15] $end
$var reg 1 :H rWordsRecvdAdv[14] $end
$var reg 1 :I rWordsRecvdAdv[13] $end
$var reg 1 :J rWordsRecvdAdv[12] $end
$var reg 1 :K rWordsRecvdAdv[11] $end
$var reg 1 :L rWordsRecvdAdv[10] $end
$var reg 1 :M rWordsRecvdAdv[9] $end
$var reg 1 :N rWordsRecvdAdv[8] $end
$var reg 1 :O rWordsRecvdAdv[7] $end
$var reg 1 :P rWordsRecvdAdv[6] $end
$var reg 1 :Q rWordsRecvdAdv[5] $end
$var reg 1 :R rWordsRecvdAdv[4] $end
$var reg 1 :S rWordsRecvdAdv[3] $end
$var reg 1 :T rWordsRecvdAdv[2] $end
$var reg 1 :U rWordsRecvdAdv[1] $end
$var reg 1 :V rWordsRecvdAdv[0] $end
$var reg 1 :W LEN[31] $end
$var reg 1 :X LEN[30] $end
$var reg 1 :Y LEN[29] $end
$var reg 1 :Z LEN[28] $end
$var reg 1 :[ LEN[27] $end
$var reg 1 :\ LEN[26] $end
$var reg 1 :] LEN[25] $end
$var reg 1 :^ LEN[24] $end
$var reg 1 :_ LEN[23] $end
$var reg 1 :` LEN[22] $end
$var reg 1 :a LEN[21] $end
$var reg 1 :b LEN[20] $end
$var reg 1 :c LEN[19] $end
$var reg 1 :d LEN[18] $end
$var reg 1 :e LEN[17] $end
$var reg 1 :f LEN[16] $end
$var reg 1 :g LEN[15] $end
$var reg 1 :h LEN[14] $end
$var reg 1 :i LEN[13] $end
$var reg 1 :j LEN[12] $end
$var reg 1 :k LEN[11] $end
$var reg 1 :l LEN[10] $end
$var reg 1 :m LEN[9] $end
$var reg 1 :n LEN[8] $end
$var reg 1 :o LEN[7] $end
$var reg 1 :p LEN[6] $end
$var reg 1 :q LEN[5] $end
$var reg 1 :r LEN[4] $end
$var reg 1 :s LEN[3] $end
$var reg 1 :t LEN[2] $end
$var reg 1 :u LEN[1] $end
$var reg 1 :v LEN[0] $end
$var reg 1 :w rAlmostAllRecvd $end
$var reg 1 :x rLenEQ0Hi $end
$var reg 1 :y rLenLE4Lo $end
$upscope $end
$scope module writer $end
$var reg 1 :z rMainState[7] $end
$var reg 1 :{ rMainState[6] $end
$var reg 1 :| rMainState[5] $end
$var reg 1 :} rMainState[4] $end
$var reg 1 :~ rMainState[3] $end
$var reg 1 ;! rMainState[2] $end
$var reg 1 ;" rMainState[1] $end
$var reg 1 ;# rMainState[0] $end
$var reg 1 ;$ rOffLast[31] $end
$var reg 1 ;% rOffLast[30] $end
$var reg 1 ;& rOffLast[29] $end
$var reg 1 ;' rOffLast[28] $end
$var reg 1 ;( rOffLast[27] $end
$var reg 1 ;) rOffLast[26] $end
$var reg 1 ;* rOffLast[25] $end
$var reg 1 ;+ rOffLast[24] $end
$var reg 1 ;, rOffLast[23] $end
$var reg 1 ;- rOffLast[22] $end
$var reg 1 ;. rOffLast[21] $end
$var reg 1 ;/ rOffLast[20] $end
$var reg 1 ;0 rOffLast[19] $end
$var reg 1 ;1 rOffLast[18] $end
$var reg 1 ;2 rOffLast[17] $end
$var reg 1 ;3 rOffLast[16] $end
$var reg 1 ;4 rOffLast[15] $end
$var reg 1 ;5 rOffLast[14] $end
$var reg 1 ;6 rOffLast[13] $end
$var reg 1 ;7 rOffLast[12] $end
$var reg 1 ;8 rOffLast[11] $end
$var reg 1 ;9 rOffLast[10] $end
$var reg 1 ;: rOffLast[9] $end
$var reg 1 ;; rOffLast[8] $end
$var reg 1 ;< rOffLast[7] $end
$var reg 1 ;= rOffLast[6] $end
$var reg 1 ;> rOffLast[5] $end
$var reg 1 ;? rOffLast[4] $end
$var reg 1 ;@ rOffLast[3] $end
$var reg 1 ;A rOffLast[2] $end
$var reg 1 ;B rOffLast[1] $end
$var reg 1 ;C rOffLast[0] $end
$var reg 1 ;D rWordsEQ0 $end
$var reg 1 ;E rStarted $end
$var reg 1 ;F rDoneLen[31] $end
$var reg 1 ;G rDoneLen[30] $end
$var reg 1 ;H rDoneLen[29] $end
$var reg 1 ;I rDoneLen[28] $end
$var reg 1 ;J rDoneLen[27] $end
$var reg 1 ;K rDoneLen[26] $end
$var reg 1 ;L rDoneLen[25] $end
$var reg 1 ;M rDoneLen[24] $end
$var reg 1 ;N rDoneLen[23] $end
$var reg 1 ;O rDoneLen[22] $end
$var reg 1 ;P rDoneLen[21] $end
$var reg 1 ;Q rDoneLen[20] $end
$var reg 1 ;R rDoneLen[19] $end
$var reg 1 ;S rDoneLen[18] $end
$var reg 1 ;T rDoneLen[17] $end
$var reg 1 ;U rDoneLen[16] $end
$var reg 1 ;V rDoneLen[15] $end
$var reg 1 ;W rDoneLen[14] $end
$var reg 1 ;X rDoneLen[13] $end
$var reg 1 ;Y rDoneLen[12] $end
$var reg 1 ;Z rDoneLen[11] $end
$var reg 1 ;[ rDoneLen[10] $end
$var reg 1 ;\ rDoneLen[9] $end
$var reg 1 ;] rDoneLen[8] $end
$var reg 1 ;^ rDoneLen[7] $end
$var reg 1 ;_ rDoneLen[6] $end
$var reg 1 ;` rDoneLen[5] $end
$var reg 1 ;a rDoneLen[4] $end
$var reg 1 ;b rDoneLen[3] $end
$var reg 1 ;c rDoneLen[2] $end
$var reg 1 ;d rDoneLen[1] $end
$var reg 1 ;e rDoneLen[0] $end
$var reg 1 ;f rTxErrd $end
$var reg 1 ;g rNotRequesting $end
$var reg 1 ;h rTxReqAck $end
$var reg 1 ;i rTxState[7] $end
$var reg 1 ;j rTxState[6] $end
$var reg 1 ;k rTxState[5] $end
$var reg 1 ;l rTxState[4] $end
$var reg 1 ;m rTxState[3] $end
$var reg 1 ;n rTxState[2] $end
$var reg 1 ;o rTxState[1] $end
$var reg 1 ;p rTxState[0] $end
$var reg 1 ;q SG_ELEM_RDY $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module intr $end
$var reg 1 ;r VECT_0[31] $end
$var reg 1 ;s VECT_0[30] $end
$var reg 1 ;t VECT_0[29] $end
$var reg 1 ;u VECT_0[28] $end
$var reg 1 ;v VECT_0[27] $end
$var reg 1 ;w VECT_0[26] $end
$var reg 1 ;x VECT_0[25] $end
$var reg 1 ;y VECT_0[24] $end
$var reg 1 ;z VECT_0[23] $end
$var reg 1 ;{ VECT_0[22] $end
$var reg 1 ;| VECT_0[21] $end
$var reg 1 ;} VECT_0[20] $end
$var reg 1 ;~ VECT_0[19] $end
$var reg 1 <! VECT_0[18] $end
$var reg 1 <" VECT_0[17] $end
$var reg 1 <# VECT_0[16] $end
$var reg 1 <$ VECT_0[15] $end
$var reg 1 <% VECT_0[14] $end
$var reg 1 <& VECT_0[13] $end
$var reg 1 <' VECT_0[12] $end
$var reg 1 <( VECT_0[11] $end
$var reg 1 <) VECT_0[10] $end
$var reg 1 <* VECT_0[9] $end
$var reg 1 <+ VECT_0[8] $end
$var reg 1 <, VECT_0[7] $end
$var reg 1 <- VECT_0[6] $end
$var reg 1 <. VECT_0[5] $end
$var reg 1 </ VECT_0[4] $end
$var reg 1 <0 VECT_0[3] $end
$var reg 1 <1 VECT_0[2] $end
$var reg 1 <2 VECT_0[1] $end
$var reg 1 <3 VECT_0[0] $end
$var reg 1 <4 VECT_1[31] $end
$var reg 1 <5 VECT_1[30] $end
$var reg 1 <6 VECT_1[29] $end
$var reg 1 <7 VECT_1[28] $end
$var reg 1 <8 VECT_1[27] $end
$var reg 1 <9 VECT_1[26] $end
$var reg 1 <: VECT_1[25] $end
$var reg 1 <; VECT_1[24] $end
$var reg 1 << VECT_1[23] $end
$var reg 1 <= VECT_1[22] $end
$var reg 1 <> VECT_1[21] $end
$var reg 1 <? VECT_1[20] $end
$var reg 1 <@ VECT_1[19] $end
$var reg 1 <A VECT_1[18] $end
$var reg 1 <B VECT_1[17] $end
$var reg 1 <C VECT_1[16] $end
$var reg 1 <D VECT_1[15] $end
$var reg 1 <E VECT_1[14] $end
$var reg 1 <F VECT_1[13] $end
$var reg 1 <G VECT_1[12] $end
$var reg 1 <H VECT_1[11] $end
$var reg 1 <I VECT_1[10] $end
$var reg 1 <J VECT_1[9] $end
$var reg 1 <K VECT_1[8] $end
$var reg 1 <L VECT_1[7] $end
$var reg 1 <M VECT_1[6] $end
$var reg 1 <N VECT_1[5] $end
$var reg 1 <O VECT_1[4] $end
$var reg 1 <P VECT_1[3] $end
$var reg 1 <Q VECT_1[2] $end
$var reg 1 <R VECT_1[1] $end
$var reg 1 <S VECT_1[0] $end
$var reg 1 <T INTR_MSI_REQUEST $end
$var reg 1 <U rVect0[31] $end
$var reg 1 <V rVect0[30] $end
$var reg 1 <W rVect0[29] $end
$var reg 1 <X rVect0[28] $end
$var reg 1 <Y rVect0[27] $end
$var reg 1 <Z rVect0[26] $end
$var reg 1 <[ rVect0[25] $end
$var reg 1 <\ rVect0[24] $end
$var reg 1 <] rVect0[23] $end
$var reg 1 <^ rVect0[22] $end
$var reg 1 <_ rVect0[21] $end
$var reg 1 <` rVect0[20] $end
$var reg 1 <a rVect0[19] $end
$var reg 1 <b rVect0[18] $end
$var reg 1 <c rVect0[17] $end
$var reg 1 <d rVect0[16] $end
$var reg 1 <e rVect0[15] $end
$var reg 1 <f rVect0[14] $end
$var reg 1 <g rVect0[13] $end
$var reg 1 <h rVect0[12] $end
$var reg 1 <i rVect0[11] $end
$var reg 1 <j rVect0[10] $end
$var reg 1 <k rVect0[9] $end
$var reg 1 <l rVect0[8] $end
$var reg 1 <m rVect0[7] $end
$var reg 1 <n rVect0[6] $end
$var reg 1 <o rVect0[5] $end
$var reg 1 <p rVect0[4] $end
$var reg 1 <q rVect0[3] $end
$var reg 1 <r rVect0[2] $end
$var reg 1 <s rVect0[1] $end
$var reg 1 <t rVect0[0] $end
$var reg 1 <u rVect1[31] $end
$var reg 1 <v rVect1[30] $end
$var reg 1 <w rVect1[29] $end
$var reg 1 <x rVect1[28] $end
$var reg 1 <y rVect1[27] $end
$var reg 1 <z rVect1[26] $end
$var reg 1 <{ rVect1[25] $end
$var reg 1 <| rVect1[24] $end
$var reg 1 <} rVect1[23] $end
$var reg 1 <~ rVect1[22] $end
$var reg 1 =! rVect1[21] $end
$var reg 1 =" rVect1[20] $end
$var reg 1 =# rVect1[19] $end
$var reg 1 =$ rVect1[18] $end
$var reg 1 =% rVect1[17] $end
$var reg 1 =& rVect1[16] $end
$var reg 1 =' rVect1[15] $end
$var reg 1 =( rVect1[14] $end
$var reg 1 =) rVect1[13] $end
$var reg 1 =* rVect1[12] $end
$var reg 1 =+ rVect1[11] $end
$var reg 1 =, rVect1[10] $end
$var reg 1 =- rVect1[9] $end
$var reg 1 =. rVect1[8] $end
$var reg 1 =/ rVect1[7] $end
$var reg 1 =0 rVect1[6] $end
$var reg 1 =1 rVect1[5] $end
$var reg 1 =2 rVect1[4] $end
$var reg 1 =3 rVect1[3] $end
$var reg 1 =4 rVect1[2] $end
$var reg 1 =5 rVect1[1] $end
$var reg 1 =6 rVect1[0] $end
$var reg 1 =7 VECT_RST[31] $end
$var reg 1 =8 VECT_RST[30] $end
$var reg 1 =9 VECT_RST[29] $end
$var reg 1 =: VECT_RST[28] $end
$var reg 1 =; VECT_RST[27] $end
$var reg 1 =< VECT_RST[26] $end
$var reg 1 == VECT_RST[25] $end
$var reg 1 => VECT_RST[24] $end
$var reg 1 =? VECT_RST[23] $end
$var reg 1 =@ VECT_RST[22] $end
$var reg 1 =A VECT_RST[21] $end
$var reg 1 =B VECT_RST[20] $end
$var reg 1 =C VECT_RST[19] $end
$var reg 1 =D VECT_RST[18] $end
$var reg 1 =E VECT_RST[17] $end
$var reg 1 =F VECT_RST[16] $end
$var reg 1 =G VECT_RST[15] $end
$var reg 1 =H VECT_RST[14] $end
$var reg 1 =I VECT_RST[13] $end
$var reg 1 =J VECT_RST[12] $end
$var reg 1 =K VECT_RST[11] $end
$var reg 1 =L VECT_RST[10] $end
$var reg 1 =M VECT_RST[9] $end
$var reg 1 =N VECT_RST[8] $end
$var reg 1 =O VECT_RST[7] $end
$var reg 1 =P VECT_RST[6] $end
$var reg 1 =Q VECT_RST[5] $end
$var reg 1 =R VECT_RST[4] $end
$var reg 1 =S VECT_RST[3] $end
$var reg 1 =T VECT_RST[2] $end
$var reg 1 =U VECT_RST[1] $end
$var reg 1 =V VECT_RST[0] $end
$var reg 1 =W VECT_0_RST $end
$var reg 1 =X VECT_1_RST $end
$var reg 1 =Y RX_SG_BUF_RECVD[0] $end
$var reg 1 =Z RX_TXN_DONE[0] $end
$var reg 1 =[ TX_SG_BUF_RECVD[0] $end
$var reg 1 =\ TX_TXN[0] $end
$var reg 1 =] TX_TXN_DONE[0] $end
$var reg 1 =^ INTR_MSI_RDY $end
$scope module intrCtlr $end
$var reg 1 =_ INTR $end
$var reg 1 =` INTR_DONE $end
$upscope $end
$upscope $end
$scope module reg_inst $end
$var reg 1 =a wReqChnl[0] $end
$var reg 1 =b wReqFieldDemux[15] $end
$var reg 1 =c wReqFieldDemux[14] $end
$var reg 1 =d wReqFieldDemux[13] $end
$var reg 1 =e wReqFieldDemux[12] $end
$var reg 1 =f wReqFieldDemux[11] $end
$var reg 1 =g wReqFieldDemux[10] $end
$var reg 1 =h wReqFieldDemux[9] $end
$var reg 1 =i wReqFieldDemux[8] $end
$var reg 1 =j wReqFieldDemux[7] $end
$var reg 1 =k wReqFieldDemux[6] $end
$var reg 1 =l wReqFieldDemux[5] $end
$var reg 1 =m wReqFieldDemux[4] $end
$var reg 1 =n wReqFieldDemux[3] $end
$var reg 1 =o wReqFieldDemux[2] $end
$var reg 1 =p wReqFieldDemux[1] $end
$var reg 1 =q wReqFieldDemux[0] $end
$scope module field_demux $end
$var reg 1 =r RD_DATA[15] $end
$var reg 1 =s RD_DATA[14] $end
$var reg 1 =t RD_DATA[13] $end
$var reg 1 =u RD_DATA[12] $end
$var reg 1 =v RD_DATA[11] $end
$var reg 1 =w RD_DATA[10] $end
$var reg 1 =x RD_DATA[9] $end
$var reg 1 =y RD_DATA[8] $end
$var reg 1 =z RD_DATA[7] $end
$var reg 1 ={ RD_DATA[6] $end
$var reg 1 =| RD_DATA[5] $end
$var reg 1 =} RD_DATA[4] $end
$var reg 1 =~ RD_DATA[3] $end
$var reg 1 >! RD_DATA[2] $end
$var reg 1 >" RD_DATA[1] $end
$var reg 1 ># RD_DATA[0] $end
$var reg 1 >$ WR_DATA[0] $end
$var reg 1 >% WR_SEL[3] $end
$var reg 1 >& WR_SEL[2] $end
$var reg 1 >' WR_SEL[1] $end
$var reg 1 >( WR_SEL[0] $end
$upscope $end
$scope module tx_len_ready_demux $end
$var reg 1 >) RD_DATA[0] $end
$var reg 1 >* WR_DATA[0] $end
$var reg 1 >+ WR_SEL[0] $end
$upscope $end
$scope module rxr_input_register $end
$var reg 1 >, RD_DATA_VALID $end
$var reg 1 >- WR_DATA_VALID $end
$upscope $end
$upscope $end
$scope module tx_mux_inst $end
$scope module tx_mux_128_inst $end
$var reg 1 >. WR_DATA_REN[0] $end
$var reg 1 >/ rCapState[3] $end
$var reg 1 >0 rCapState[2] $end
$var reg 1 >1 rCapState[1] $end
$var reg 1 >2 rCapState[0] $end
$var reg 1 >3 rMainState $end
$var reg 1 >4 TXR_META_READY $end
$var reg 1 >5 rCapIsWr $end
$var reg 1 >6 rCapChnl[3] $end
$var reg 1 >7 rCapChnl[2] $end
$var reg 1 >8 rCapChnl[1] $end
$var reg 1 >9 rCapChnl[0] $end
$var reg 1 >: rCountDone $end
$var reg 1 >; wRdAck $end
$var reg 1 >< rIsWr $end
$var reg 1 >= rWrChnl[3] $end
$var reg 1 >> rWrChnl[2] $end
$var reg 1 >? rWrChnl[1] $end
$var reg 1 >@ rWrChnl[0] $end
$var reg 1 >A rRdChnl[3] $end
$var reg 1 >B rRdChnl[2] $end
$var reg 1 >C rRdChnl[1] $end
$var reg 1 >D rRdChnl[0] $end
$var reg 1 >E rCapAddr64 $end
$var reg 1 >F rCapLen[9] $end
$var reg 1 >G rCapLen[8] $end
$var reg 1 >H rCapLen[7] $end
$var reg 1 >I rCapLen[6] $end
$var reg 1 >J rCapLen[5] $end
$var reg 1 >K rCapLen[4] $end
$var reg 1 >L rCapLen[3] $end
$var reg 1 >M rCapLen[2] $end
$var reg 1 >N rCapLen[1] $end
$var reg 1 >O rCapLen[0] $end
$scope module selRd $end
$var reg 1 >P REQ $end
$var reg 1 >Q REQ_ALL[0] $end
$var reg 1 >R rReqChnl[3] $end
$var reg 1 >S rReqChnl[2] $end
$var reg 1 >T rReqChnl[1] $end
$var reg 1 >U rReqChnl[0] $end
$upscope $end
$scope module selWr $end
$var reg 1 >V REQ $end
$var reg 1 >W REQ_ALL[0] $end
$var reg 1 >X rReqChnl[3] $end
$var reg 1 >Y rReqChnl[2] $end
$var reg 1 >Z rReqChnl[1] $end
$var reg 1 >[ rReqChnl[0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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#5000
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