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| Location of the zip with the quartus project, scans and this note: | |
| https://drive.google.com/file/d/19l7rQpiQJmDnbOJQavnp8BZulNxUG0uI/view?usp=sharing | |
| Power | |
| I injected 5V on C60 (Fat ceramic cap , on top lower right corner near the sodimm edge) | |
| The Module needs a fair ammount of current to start up properly. I had my lab supply at 3A current | |
| limit, with the original config bitstream off the config prom on the module it draws about 700mA after startup |
captain-amygdala
/ mooncell_c120.lpf
Last active
April 11, 2023 20:57
Lattice LPF Pinout for the Mooncell C120 LED receiver module
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| #### Claude Schwarz 26.03.2023 | |
| #### Mooncell C120 | |
| #### | |
| #### SDRAM DQM lines and CE are hardwired to ground, CKE is hardwired to VCC | |
| #### PHY Clock is 125MHz, on the PHY0 and PHY1 RXCLK inputs | |
| #### 25MHz Clock on CLK25 | |
| #### MDIO and RESET is shared between both PHYs | |
| #### FLASH Clock, if needed in user logic, needs to be enabled trough USRMCLK | |
| #### The INPUT_KEY_RC Pin is filtered with a RC combination | |
| #### The GPIO Connectors are named after their pins on the connector. |