vhdl_instance.py

def VHDL_ENTITY(clock, reset, x, y, z):
    z.driven = True
    @always(clock, reset, x, y)
    def logic():
        pass
    return logic
VHDL_ENTITY.vhdl_instance = "VHDL_INSTANCE_NAME"

def m_top(clock, reset, x, y, z):
    g = VHDL_ENTITY(clock, reset, x, y, z)
    return g

clock = Signal(bool(0))
reset = ResetSignal(0, 0, True)
x,y,z = [Signal(intbv(0)[8:]) for _ in range(3)]
toVHDL(m_top, clock, reset, x, y, z)