MyHDL Slice Signal Example

slcsig.py

from random import randint
from myhdl import *

def m_random_assign(clock, reset, xb):
    Xc = randint(0, 1)
    print(type(xb), xb)
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        xb.next = Xc
    return rtl

def m_top(clock, reset, x):
    g = [m_random_assign(clock, reset, x(ii)) 
        for ii in range(len(x))]
    return g

clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
x = Signal(intbv(0)[16:])

tbdut = m_top(clock, reset, x)
@instance
def tbstim():
    reset.next = not reset.active
    for ii in range(10):
        clock.next = True
        yield delay(3)
        clock.next = False
        print(x)

Simulation((tbdut, tbstim,)).run()
toVHDL(m_top, clock, reset, x)