A MyHDL issue (inconsistency/bug) when assigning an interface attribute to a ShadowSignal.

a_shadow_bit_test.py

import myhdl
print(myhdl.__version__)
from myhdl import *

#------------------------------------------------------------------------
def m_shadow_bittest(clock, sdi, sdo):
    """
    This module demostrates a ShadowSignal (slice) of an element
    in a list-of-signals is converted as a constant
    """
    a = [Signal(intbv(0)[8:]),Signal(intbv(0)[8:])]
    b = Signal(intbv(0)[8:])

    bittest = a[0](0)
    
    @always(clock.posedge)
    def rtl_in():
        a.next = concat(a[0][7:], sdi)
        sdo.next = b[7]

    @always(clock.posedge)
    def rtl():
        if bittest:
            b.next = 1
        else:
            b.next = 0

    return rtl_in, rtl

#------------------------------------------------------------------------
class A(object):
    def __init__(self):
        self.X = [Signal(intbv(0)[8:]), Signal(intbv(0)[8:])]
        self.X0 = self.X[0](0)


def logic(clk, a, b):
    """
    This module is a modified version of an example that shows a 
    ShadowSignal (slice) of an element in a list-of-signals in an 
    interface is converted as a constant.  A local reference can 
    be used to work-around this issue.
    """
    # local reference to the bit to test
    x = a.X[0]
    bittest = x(0)

    @always(clk.posedge)
    def proc():
        if bittest: #a.X0:
            b.next = 1
        else:
            b.next = 0
            a.X[0].next = 1
    return proc


def m_logic_top(clk, sdi, sdo):
    """ Simple wrapper around "logic" """
    b = Signal(intbv(0)[8:])
    a = A()

    @always(clk.posedge)
    def rtl_assign():
        a.X[0].next = concat(a.X[0][7:], sdi)
        sdo.next = b[7]

    glogic = logic(clk, a, b)
    
    return rtl_assign, glogic


#------------------------------------------------------------------------
# convert the above examples 
clock = Signal(bool(0))
sdi,sdo = Signal(bool(0)),Signal(bool(0))
toVerilog(m_shadow_bittest, clock, sdi, sdo)
if not ('0.8' in myhdl.__version__):
    toVerilog(m_logic_top, clock, sdi, sdo)

m_logic_top.v

// File: m_logic_top.v
// Generated by MyHDL 0.9dev
// Date: Wed Feb 18 08:08:04 2015


`timescale 1ns/10ps

module m_logic_top (
    clk,
    sdi,
    sdo
);


input clk;
input sdi;
output sdo;
reg sdo;

reg [7:0] b = 0;

reg [7:0] a_X [0:2-1];




always @(posedge clk) begin: M_LOGIC_TOP_RTL_ASSIGN
    a_X[0] <= {a_X[0][7-1:0], sdi};
    sdo <= b[7];
end


always @(posedge clk) begin: M_LOGIC_TOP_GLOGIC_PROC
    if (glogic_x[0]) begin
        b <= 1;
    end
    else begin
        b <= 0;
        a_X[0] <= 1;
    end
end

endmodule

m_shadow_bittest.v

// File: m_shadow_bittest.v
// Generated by MyHDL 0.9dev
// Date: Wed Feb 18 08:06:17 2015


`timescale 1ns/10ps

module m_shadow_bittest (
    clock,
    sdi,
    sdo
);


input clock;
input sdi;
output sdo;
reg sdo;

reg [7:0] b = 0;

reg [7:0] a [0:2-1];




always @(posedge clock) begin: M_SHADOW_BITTEST_RTL_IN
    a <= {a[0][7-1:0], sdi};
    sdo <= b[7];
end


always @(posedge clock) begin: M_SHADOW_BITTEST_RTL
    if (False) begin
        b <= 1;
    end
    else begin
        b <= 0;
    end
end

endmodule

A MyHDL issue (inconsistency/bug) when assigning an interface attribute to a ShadowSignal. The ShadowSignal is treated as a constant and not as a signal(?). There is a workaround and that is to locally access the item in the list and then create the ShadowSignal of the bit desired.

This appears to be a ShadowSIgnal issue and existed in 0.8.1. The "m_shadow_bittest" converts with a constant in 0.8.1 and 0.9-dev.