RAM_byte_enable_user.py

from myhdl import *

instance_count = 0

def RAM_byte_enable_user(wdata, waddr, we, rdata, clk):
    """ RAM with byte enable writes
    """
    global instance_count
    assert len(wdata)/8 == len(we)
    # make the memory as large as the address space and the width
    # of data
    mem = [Signal(intbv()[len(wdata):0]) for i in range(waddr.max)]

    data_width = len(wdata)
    num_banks = len(we)
    mem_depth = len(mem)
    instance_count += 1
    
    @always(clk.posedge)
    def impl():
        for i in range(num_banks):
            if we[i]:
                mem[waddr].next[(i+1)*8:i*8] = wdata[(i+1)*8:i*8]
        
    @always(clk.posedge)
    def impl_read():
        rdata.next = mem[waddr]
    rdata.driven = True
        
    return instances()

RAM_byte_enable_user.verilog_code = \
"""
ram_verilog_version
  #(.width($data_width), .num_enable($num_banks), .depth($mem_depth))
  U$instance_count ($wdata, $waddr, $we, $rdata, $clk);
"""                                     

RAM_byte_enable_user.v

// File: RAM_byte_enable_user.v
// Generated by MyHDL 1.0dev
// Date: Mon Jul 27 07:27:00 2015


`timescale 1ns/10ps

module RAM_byte_enable_user (
    wdata,
    waddr,
    we,
    rdata,
    clk
);
// RAM with byte enable writes
//     

input [31:0] wdata;
input [11:0] waddr;
input [3:0] we;
output [31:0] rdata;
wire [31:0] rdata;
input clk;

ram_verilog_version
  #(.width(32), .num_enable(4), .depth(4096))
  U1 (wdata, waddr, we, rdata, clk);

endmodule