regfile.py

#!/bin/env python
 
from myhdl import *
 
class RegFile(object):
    def __init__(self):
        # actual memory storage
        self._mem   = [Signal(intbv(0)[8:]) for i in xrange(20)]
 
        # named registers port for reading
        self.regA  = ConcatSignal(*[self._mem[0+i]    for i in 0,1])
        self.regB  = ConcatSignal(*[self._mem[2+i]    for i in 0,1])
 
        # named registers port for writing
        self.regAw = Signal(intbv(0)[16:])

        # define where the named write registers should go
        self.writemap = [(self.regAw(16,8), 0,),
                         (self.regAw(8,0),  1,)]
 
    def _write(self, clk, reg, idx):
        @always(clk.posedge)
        def rtl_write():
            self._mem[idx].next = reg
        return rtl_write

 
def controller(clk, rst, X, Z):
    rf = RegFile()
 
    writelist = []
    for reg,idx in rf.writemap:
        writelist += [rf._write(clk, reg, idx)]

    @always_comb
    def io():
        rf.regAw.next = X
        Z.next = rf.regA + rf.regB
 
    return io, writelist
 

def test():
    clk = Signal(False)
    rst = ResetSignal(1, active=0, async=True)
    x = Signal(intbv(0)[16:])
    y = Signal(intbv(0)[16:])
 
 
    toVerilog.timescale = '1ns/1ps'
    toVerilog(controller, clk, rst, x, y)
 
test()