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@cfelton
Last active June 16, 2019 14:05
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from myhdl import *
def top(sda, scl, sda_i, sda_o, scl_i, scl_o):
"""Simple I2C bi-dir converter.
This example will break the I2C bi-directional signals into
uni-dir explicit signals.
"""
sda_d = sda.driver()
scl_d = scl.driver()
@always_comb
def hdl():
sda_i.next = sda
sda_d.next = False if not sda_o else None
scl_i.next = scl
scl_d.next = False if not scl_o else None
return hdl
def convert():
clk = Signal(False)
rst = Signal(False)
sda = TristateSignal(True)
scl = TristateSignal(True)
sda_i = Signal(False)
sda_o = Signal(False)
scl_i = Signal(False)
scl_o = Signal(False)
toVerilog(top, sda, scl, sda_i, sda_o, scl_i, scl_o)
toVHDL(top, sda, scl, sda_i, sda_o, scl_i, scl_o)
if __name__ == '__main__':
convert()
@raaees
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raaees commented Jun 16, 2019

is this code complete?

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