The following demonstrates a top-level interface conversion issue.

myhdl_issue_nnn.py

import myhdl
from myhdl import Signal, intbv, always_comb


class Intf1(object):
    def __init__(self):
        self.a = Signal(intbv(0, min=0, max=2))
        self.b = Signal(intbv(0, min=0, max=4))
        self.c = Signal(intbv(0, min=0, max=8))


class Intf2(object):
    def __init__(self):
        self.b = Signal(intbv(0, min=0, max=4))
        self.c = Signal(intbv(0, min=0, max=8))


def assign(a, b):
    @always_comb
    def beh_assign():
        b.next = a
    return beh_assign

def top_level_assign(intf_in, intf_out):
    m1 = assign(intf_in.b, intf_out.b)
    m2 = assign(intf_in.c, intf_out.c)
    return  m1, m2


def convert():
    if1, if2 = Intf1(), Intf2()
    myhdl.toVerilog(top_level_assign, if1, if2)


if __name__ == '__main__':
    convert()

top_level_assign.v

// File: top_level_assign.v
// Generated by MyHDL 1.0dev
// Date: Thu Feb 25 09:06:48 2016


`timescale 1ns/10ps

module top_level_assign (
    b,
    b,
    a,
    a,
    intf_in_a
);


output [2:0] b;
wire [2:0] b;
output [2:0] b;
wire [2:0] b;
input [2:0] a;
input [2:0] a;
input [0:0] intf_in_a;

assign b = a;
assign b = a;

endmodule