testing_example.py

from __future__ import division
from __future__ import print_function

from myhdl import *

# my module
def m_add(clock, reset, x, y, z):
    """ y = x + 1, z = x + 3
    """
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        y.next = x + 1
        z.next = x + 3

    return rtl



def testbench():
    clock = Signal(bool(0))
    reset = ResetSignal(0, active=0, async=True)

    x = Signal(intbv(0, min=-16, max=16))
    outs = [Signal(intbv(0, min=-16, max=19)) for _ in range(2)]
    
    tbdut = m_add(clock, reset, x, *outs)

    @always(delay(5))
    def tbclk():
        clock.next = not clock

    # values to test, the output is delayed the input
    # the first output is the default 0 input
    test_inputs = range(-16, 16)
    test_outs = [[1,3,]] + [[t+1, t+3,] for t in test_inputs]

    @instance
    def tbstim():
        reset.next = reset.active
        yield delay(100)
        reset.next = not reset.active
        yield clock.posedge
        for ii, oo in zip(test_inputs, test_outs):
            x.next = ii
            yield clock.posedge
            # not a separate check module
            print(ii, oo, map(int, outs))
            assert oo == map(int, outs)
        raise StopSimulation
    
    Simulation((tbdut, tbclk, tbstim)).run() 


testbench()