Mux_better.py

from myhdl import *

class Mux(object):
    def __init__(self, inputs, output, sel):
        self.nports = len(inputs)
        self.inputs = inputs
        self.output = output
        self.sel = sel
        
    def logic(self):
        """ 
        note note convertible, to make convertible, move ports from
        the object instantiation to the MyHDL module (function that 
        returns MyHDL generators).
        """
        @always_comb
        def rtl():
            self.output = self.inputs[self.sel]
        return rtl

Mux_messy.py

class Mux( Model ):

  def __init__( s, nbits = 1, nports = 2 ):

    s.nports = nports
    s.nsel   = get_sel_nbits( nports )

    s.in_ = [ InPort( nbits ) for x in xrange( nports ) ]
    s.sel = InPort  ( s.nsel )
    s.out = OutPort ( nbits )

  def elaborate_logic( s ):
    @s.combinational
    def comb_logic():
      assert s.sel < s.nports
      s.out.v = s.in_[ s.sel ]