initial value support conversion error

ivs_mem.py

import myhdl as hdl
from myhdl import Signal, ResetSignal, intbv, always_seq

@hdl.block
def test_mem_ivs_convert(clock, reset, wr, wrd, rdd, addr):
    return memory(clock, reset, wr, wrd, rdd, addr)

@hdl.block
def memory(clock, reset, wr, wrd, rdd, addr):
    mem = [Signal(intbv(0, min=wrd.min, max=wrd.max)) 
        for _ in range(addr.max)]    
    @always_seq(clock.posedge, reset=reset)
    def beh_mem():
        rdd.next = mem[addr]
        if wr:
            mem[addr].next = wrd
    return beh_mem
            
memory.verilog_code = """
    initial begin
        $mem = $$readmem("initial_values.mem");
    end
"""

clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
wr = Signal(bool(0))
wrd = Signal(intbv(0, min=0, max=32))
rdd = Signal(intbv(0, min=0, max=32))
addr = Signal(intbv(0, min=0, max=16))

inst = test_mem_ivs_convert(clock, reset, wr, wrd, rdd, addr)
inst.convert()

test_mem_ivs_convert.v

// File: test_mem_ivs_convert.v
// Generated by MyHDL 1.0dev
// Date: Fri Mar  9 05:54:45 2018


`timescale 1ns/10ps

module test_mem_ivs_convert (
    clock,
    reset,
    wr,
    wrd,
    rdd,
    addr
);


input clock;
input reset;
input wr;
input [4:0] wrd;
input [4:0] rdd;
input [3:0] addr;





    initial begin
        [Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0)), Signal(intbv(0))] = $readmem("initial_values.mem");
    end

endmodule