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@cfelton
Last active May 9, 2016 12:40
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from myhdl import Signal, intbv
class SomeInterface(object):
def __init__(self, clock):
self.clock = clock
self.datain = Signa(intbv(0)[8:])
self.dataout = Signal(intbv(0)[8:])
self.data_valid = Signal(bool(0))
def writetrans(self, data):
self.datain.next = data
self.data_valid.next = True
yield self.clock
self.data_valid.next = False
def transactors_in_use():
intf = SomeInterface()
@instance
def testbench_driver():
yield intf.writetrans(4)
yield intf.writetrans(5)
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