cfelton

def rgb2ycbcr(rgb, ycbcr, clock, reset):
    """ A RGB to YCbCr converter with reset.

    Arguments:
        rgb: red, green, blue interface
               r: input 8-bit unsigned value in range of 0-255
               g: input 8-bit unsigned value in range of 0-255
               b: input 8-bit unsigned value in range of 0-255

cfelton

pix_t median(pix_t window[N])
{
    pix_t t[N], z[N];
    int ii, k, stage;
  
    // copy locally
    for(ii=0; ii<N; ii++) z[ii] = window[ii];
  
    for(stage=1; stage<=N; stage++){
        k = (stage%2==1) ? 0 : 1;

cfelton

from myhdl import Signal, intbv, always_seq


def shift_reg(clock, reset, y):

    shift = Signal(intbv(0)[len(y):])
    mask = shift.max - 1

    @always_seq(clock.posedge, reset=reset)

cfelton

from random import randint
from myhdl import *


def tristate(tri, tin, tout, en):
    """ tristate driver
    Ports:
      tri: tri-state signal
      tin: tri-state input
      tout: the signal to drive the tri-state

cfelton

import myhdl
from myhdl import Signal, intbv, instance, delay, StopSimulation


def testbench_template(args=None):
    # any code to extract argument for what is desired to be tested
  
    # instantiate all signals and interface 
  

cfelton

from myhdl import *

def array3(clock, reset, sel1, sel2, data_out):
    """ simulation only """
    # generate an array of constants
    aoc = [[cc for cc in range((ii*3)+1, (ii*3)+4)] for ii in range(3)]
    
    @always_seq(clock.posedge, reset=reset)
    def rtlreg():
        data_out.next = aoc[sel2][sel1]

cfelton

import os
from random import randint

import myhdl
from myhdl import (Signal, ResetSignal, intbv, always_seq, always,
                   always_comb, delay, instance, traceSignals, 
                   Simulation, StopSimulation)

cfelton

me = 0

class Interface:
    def __init__(self):
        self.x = Signal(bool(0))
        self.y = Signal(bool(0))

def mod_with_interface(intf):
    global me
    xi = me

cfelton

from __future__ import division
from __future__ import print_function

from random import shuffle, randint
import myhdl
from myhdl import (Signal, ResetSignal, intbv, always_seq, always,
                   delay, instance, traceSignals, Simulation)

class DataStream:

cfelton

from myhdl import *

instance_count = 0

def RAM_byte_enable_user(wdata, waddr, we, rdata, clk):
    """ RAM with byte enable writes
    """
    global instance_count
    assert len(wdata)/8 == len(we)