Created
September 18, 2019 16:54
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Attempt to reproduce firrtl-interpreter width error
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// See README.md for license details. | |
package firrtl_interpreter | |
import firrtl.CommonOptions | |
import org.scalatest.{FreeSpec, Matchers} | |
class WidthProblemSpec extends FreeSpec with Matchers { | |
"should get width right" in { | |
val input = | |
""" | |
|circuit Deep_1 : | |
| module Deep_1 : | |
| input clock : Clock | |
| input reset : UInt<1> | |
| | |
| input data : SInt<8>[4] | |
| input const_data : SInt<8>[4] | |
| output output : SInt<8>[4] | |
| output uout : SInt<9> | |
| | |
| wire inputData : SInt<8>[4] | |
| wire constInputData : SInt<8>[4] | |
| reg outputData : SInt<8>[4] clock | |
| | |
| inputData[0] <= SInt<8>(0) | |
| inputData[1] <= SInt<8>(0) | |
| inputData[3] <= SInt<8>(0) | |
| | |
| constInputData[0] <= SInt<8>(0) | |
| constInputData[1] <= SInt<8>(0) | |
| constInputData[3] <= SInt<8>(0) | |
| | |
| outputData[0] <= SInt<8>(0) | |
| outputData[1] <= SInt<8>(0) | |
| outputData[3] <= SInt<8>(0) | |
| | |
| output[0] <= SInt<8>(0) | |
| output[1] <= SInt<8>(0) | |
| output[3] <= SInt<8>(0) | |
| | |
| inputData[2] <= data[2] | |
| constInputData[2] <= const_data[2] | |
| node _T_209 = add(inputData[2], constInputData[2]) | |
| uout <= _T_209 | |
| node _T_210 = tail(_T_209, 1) | |
| node _T_211 = asSInt(_T_210) | |
| outputData[2] <= _T_211 | |
| output[2] <= outputData[2] | |
|""".stripMargin | |
val optionsManager = new InterpreterOptionsManager { | |
interpreterOptions = InterpreterOptions(showFirrtlAtLoad = true, setVerbose = true) | |
commonOptions = CommonOptions(targetDirName = "test_run_dir") | |
} | |
val tester = new InterpretiveTester(input, optionsManager) | |
tester.poke("data_2", 150) | |
tester.poke("const_data_2", 153) | |
tester.step() | |
println(s"uout ${tester.peek("uout")} -209 poked values end up being -106 -103") | |
println(s"output_2 ${tester.peek("output_2")} expecting 47 -209 with top bit lopped off") | |
tester.finish | |
} | |
} |
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