chick

// SPDX-License-Identifier: Apache-2.0

package chiseltest.tests

package gbvga

import chisel3._
import chisel3.util._
import chisel3.experimental.BundleLiterals._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}

chick

// See README.md for license details.

package firrtl_interpreter

import firrtl.CommonOptions
import org.scalatest.{FreeSpec, Matchers}

class WidthProblemSpec extends FreeSpec with Matchers {
  "should get width right" in {
    val input =

chick

;buildInfoPackage: chisel3, version: 3.2-SNAPSHOT, scalaVersion: 2.12.9, sbtVersion: 1.2.7
circuit Cache : 
  module Cache : 
    input clock : Clock
    input reset : UInt<1>
    output io : {cpu : {flip abort : UInt<1>, flip req : {valid : UInt<1>, bits : {addr : UInt<32>, data : UInt<32>, mask : UInt<4>}}, resp : {valid : UInt<1>, bits : {data : UInt<32>}}}, nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>,

chick

package bit_examples

import chisel3._
import chisel3.experimental.MultiIOModule
import chisel3.iotesters.PeekPokeTester
import chisel3.util.Cat

import org.scalatest.{FreeSpec, Matchers}

//scalastyle:off magic.number

chick

// See README.md for license details.

package runlengthencoder

import chisel3._
import chisel3.iotesters
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
import org.scalatest.{FreeSpec, Matchers}
import chisel3.util.log2Ceil

chick

// See LICENSE for license details.

package myrepl

import scala.tools.jline.console.ConsoleReader
import scala.tools.jline.console.completer._
import collection.JavaConverters._
import scala.tools.jline.{Terminal, TerminalFactory}

import scala.collection.mutable.ArrayBuffer

chick

circuit GCD :
  module GCD :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<16>, flip b : UInt<16>, flip e : UInt<1>, z : UInt<16>, v : UInt<1>}

    reg x : UInt, clock @[GCD.scala 15:15]
    reg y : UInt, clock @[GCD.scala 16:15]
    node _T_9 = gt(x, y) @[GCD.scala 18:11]
    when _T_9 : @[GCD.scala 18:16]

chick

package hardwaresort

import chisel3._
import chisel3.experimental.FixedPoint
import chisel3.internal.firrtl.KnownBinaryPoint
import chisel3.iotesters.PeekPokeTester
import chisel3.util.log2Ceil

//scalastyle:off magic.number
/**

chick

// See LICENSE for license details.

package examples

/**
  * verilator and interpreter have inconsistent behavior around reset.
  */

import java.io.File

chick

class MyBundle extends Bundle {
  val x = Bool()
  val y = UInt(8.W)
  val z = Bool()
}

object MyBundle {
  /**
    * initialize x and y but not z,
    * @return