How do I right pad an SInt

PadderSpec.scala

// See LICENSE for license details.

package simple.example

import chisel3._
import chisel3.iotesters.{PeekPokeTester, runPeekPokeTester, Backend}
import chisel3.util.{Cat, Fill}
import org.scalatest.{Matchers, FlatSpec}

class Padable(val numBits: Int, val radixPoint: Int) extends Bundle {
  val underlying = SInt(width = numBits)
  override def cloneType: this.type = {
    new Padable(numBits, radixPoint).asInstanceOf[this.type]
  }

  def padRight(padSize: Int): SInt = {
    val filled = Wire(Fill(padSize.abs, 1.U))
    Cat(underlying, filled).asSInt()
  }
}

class Padder(nb1: Int, rp1: Int, nb3: Int, rp3: Int) extends Module {
  val io = new Bundle {
    val a = new Padable(nb1, rp1)
    val c = new Padable(nb3, rp3)
  }

  io.c.underlying := io.a.padRight(4)
}

class PadderTester(c: Padder, backend: Option[Backend] = None) extends PeekPokeTester(c, _backend = backend) {
  poke(c.io.a.underlying, BigInt(5))

  expect(c.io.c.underlying, BigInt("5F", 16))
}

class PadderSpec extends FlatSpec with Matchers {
  "Padder" should "add correctly" in {
    runPeekPokeTester(() => new Padder(4, 1, 9, 5), "firrtl"){
      (c,b) => new PadderTester(c,b)} should be (true)
  }
}

/**
circuit PadderAdder : 
  module PadderAdder : 
    input clk : Clock
    input reset : UInt<1>
    output io : {a : {underlying : SInt<4>}, c : {underlying : SInt<9>}}
    
    io is invalid
    node T_5 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 20:58] 
    node T_6 = cat(T_5, T_5) @[Cat.scala 20:58] 
    wire T_7 : UInt<4> @[Cat.scala 24:22] 
    T_7 is invalid @[Cat.scala 24:22] 
    node T_8 = asUInt(io.a.underlying) @[Cat.scala 20:58] 
    node T_9 = cat(T_8, T_7) @[Cat.scala 20:58] 
    node T_10 = asSInt(T_9) @[Cat.scala 25:35] 
    io.c.underlying <= T_10 @[Cat.scala 35:19] 
    
*/